SRAM_CTRL/MAIN Simulation Results

Wednesday October 22 2025 16:03:16 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.059m	1.404ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.760s	15.916us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	30.499us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.990s	625.568us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.910s	18.659us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.540s	725.160us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	30.499us	1	1	100.00
		sram_ctrl_csr_aliasing	0.910s	18.659us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.737m	10.525ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	57.590s	2.414ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	4.079m	12.771ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.791m	6.636ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	22.682m	106.477ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	9.354m	22.933ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	35.320s	15.797ms	1	1	100.00
V2	executable	sram_ctrl_executable	6.393m	44.323ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	18.460s	1.017ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.631m	40.232ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	23.280s	742.148us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	8.730s	700.883us	1	1	100.00
		sram_ctrl_throughput_w_readback	8.650s	10.030ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	41.560s	1.699ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.220s	698.007us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.037h	703.430ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.970s	40.488us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.070s	262.872us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.070s	262.872us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.760s	15.916us	1	1	100.00
		sram_ctrl_csr_rw	0.710s	30.499us	1	1	100.00
		sram_ctrl_csr_aliasing	0.910s	18.659us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.640s	16.186us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.760s	15.916us	1	1	100.00
		sram_ctrl_csr_rw	0.710s	30.499us	1	1	100.00
		sram_ctrl_csr_aliasing	0.910s	18.659us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.640s	16.186us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	36.060s	70.441ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.750s	21.757us	0	1	0.00
		sram_ctrl_tl_intg_err	1.990s	192.754us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.750s	21.757us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.990s	192.754us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	41.560s	1.699ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	41.560s	1.699ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	30.499us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	6.393m	44.323ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	6.393m	44.323ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	6.393m	44.323ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	35.320s	15.797ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.050s	1.375ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	36.060s	70.441ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.370s	701.694us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.059m	1.404ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.059m	1.404ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	6.393m	44.323ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.750s	21.757us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	35.320s	15.797ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.750s	21.757us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.750s	21.757us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.059m	1.404ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.750s	21.757us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.270s	705.597us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.109301559470954940040252049557811477528224827531463962840227100813232413415765
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  21757227 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  21757227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---