SRAM_CTRL/RET Simulation Results

Wednesday October 22 2025 16:03:16 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.010s	84.498us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.900s	26.061us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.950s	20.400us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.410s	127.384us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.970s	36.164us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.240s	134.987us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.950s	20.400us	1	1	100.00
		sram_ctrl_csr_aliasing	0.970s	36.164us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.820s	1.134ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.710s	248.027us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.399m	42.717ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.163m	10.062ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	22.540s	491.083us	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.414m	1.648ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.110s	567.185us	1	1	100.00
V2	executable	sram_ctrl_executable	8.821m	18.236ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	47.320s	2.528ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.103m	8.987ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.450s	483.352us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	15.310s	1.943ms	1	1	100.00
		sram_ctrl_throughput_w_readback	15.300s	743.194us	1	1	100.00
V2	regwen	sram_ctrl_regwen	10.822m	222.556ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.010s	87.638us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	13.693m	17.109ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.670s	16.468us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.470s	593.799us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.470s	593.799us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.900s	26.061us	1	1	100.00
		sram_ctrl_csr_rw	0.950s	20.400us	1	1	100.00
		sram_ctrl_csr_aliasing	0.970s	36.164us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.880s	22.429us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.900s	26.061us	1	1	100.00
		sram_ctrl_csr_rw	0.950s	20.400us	1	1	100.00
		sram_ctrl_csr_aliasing	0.970s	36.164us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.880s	22.429us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.370s	1.548ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.640s	3.749us	0	1	0.00
		sram_ctrl_tl_intg_err	1.950s	748.324us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.640s	3.749us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.950s	748.324us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	10.822m	222.556ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	10.822m	222.556ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.950s	20.400us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.821m	18.236ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.821m	18.236ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.821m	18.236ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.110s	567.185us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.030s	29.021us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.370s	1.548ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.880s	107.782us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.010s	84.498us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.010s	84.498us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.821m	18.236ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.640s	3.749us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.110s	567.185us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.640s	3.749us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.640s	3.749us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.010s	84.498us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.640s	3.749us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	36.650s	1.003ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.21252964469172346246096852186381573628901171347179946231444800637727066060466
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  29021413 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  29021413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.101937887763004553466080764162542152866253101250925524526665967847371931071341
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3748860 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3748860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---