UART Simulation Results

Wednesday October 22 2025 16:03:16 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.920s	873.545us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.600s	47.760us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.740s	14.859us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.020s	173.752us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.830s	83.911us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.800s	24.838us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.740s	14.859us	1	1	100.00
		uart_csr_aliasing	0.830s	83.911us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	52.480s	127.380ms	1	1	100.00
V2	parity	uart_smoke	1.920s	873.545us	1	1	100.00
		uart_tx_rx	52.480s	127.380ms	1	1	100.00
V2	parity_error	uart_intr	1.602m	321.075ms	1	1	100.00
		uart_rx_parity_err	1.732m	158.365ms	1	1	100.00
V2	watermark	uart_tx_rx	52.480s	127.380ms	1	1	100.00
		uart_intr	1.602m	321.075ms	1	1	100.00
V2	fifo_full	uart_fifo_full	7.720s	24.385ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	16.960s	12.709ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	58.320s	53.555ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.602m	321.075ms	1	1	100.00
V2	rx_break_err	uart_intr	1.602m	321.075ms	1	1	100.00
V2	rx_timeout	uart_intr	1.602m	321.075ms	1	1	100.00
V2	perf	uart_perf	5.722m	9.419ms	0	1	0.00
V2	sys_loopback	uart_loopback	3.960s	7.467ms	1	1	100.00
V2	line_loopback	uart_loopback	3.960s	7.467ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	24.960s	18.641ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.160s	3.006ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	12.100s	7.061ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	14.570s	5.063ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	15.774m	130.516ms	1	1	100.00
V2	stress_all	uart_stress_all	9.940s	9.562ms	1	1	100.00
V2	alert_test	uart_alert_test	0.620s	13.665us	1	1	100.00
V2	intr_test	uart_intr_test	0.710s	13.697us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.070s	489.500us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.070s	489.500us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.600s	47.760us	1	1	100.00
		uart_csr_rw	0.740s	14.859us	1	1	100.00
		uart_csr_aliasing	0.830s	83.911us	1	1	100.00
		uart_same_csr_outstanding	0.860s	105.886us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.600s	47.760us	1	1	100.00
		uart_csr_rw	0.740s	14.859us	1	1	100.00
		uart_csr_aliasing	0.830s	83.911us	1	1	100.00
		uart_same_csr_outstanding	0.860s	105.886us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	0.920s	88.807us	1	1	100.00
		uart_tl_intg_err	1.040s	46.643us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.040s	46.643us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	35.770s	14.900ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.73237338775494817335692526828618518307388640316440761394638107884465881153392
      Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 18498362357 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 18545907465 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 18545917774 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 18545928083 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (161 [0xa1] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 18587153774 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 1 failures:

  • Test uart_perf has 1 failures.

    • 0.uart_perf.35278955710760554738649460999581428429445421009286575685123070021338498896372
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_perf/latest/run.log

        UVM_ERROR @   1147643 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 3346590213 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/5
        UVM_INFO @ 7930190219 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/5
        UVM_INFO @ 8252962646 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/5
        UVM_INFO @ 8493149252 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/5