AES/MASKED Simulation Results

Thursday October 23 2025 16:00:55 UTC

GitHub Revision: 1ba76ab

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	61.411us	1	1	100.00
V1	smoke	aes_smoke	2.000s	82.540us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	86.431us	1	1	100.00
V1	csr_rw	aes_csr_rw	1.000s	143.741us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	5.000s	690.742us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	142.045us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.000s	120.984us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.000s	143.741us	1	1	100.00
		aes_csr_aliasing	3.000s	142.045us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	2.000s	82.540us	1	1	100.00
		aes_config_error	3.000s	190.326us	1	1	100.00
		aes_stress	2.000s	68.254us	1	1	100.00
V2	key_length	aes_smoke	2.000s	82.540us	1	1	100.00
		aes_config_error	3.000s	190.326us	1	1	100.00
		aes_stress	2.000s	68.254us	1	1	100.00
V2	back2back	aes_stress	2.000s	68.254us	1	1	100.00
		aes_b2b	16.000s	1.687ms	1	1	100.00
V2	backpressure	aes_stress	2.000s	68.254us	1	1	100.00
V2	multi_message	aes_smoke	2.000s	82.540us	1	1	100.00
		aes_config_error	3.000s	190.326us	1	1	100.00
		aes_stress	2.000s	68.254us	1	1	100.00
		aes_alert_reset	4.000s	487.613us	1	1	100.00
V2	failure_test	aes_man_cfg_err	2.000s	81.161us	1	1	100.00
		aes_config_error	3.000s	190.326us	1	1	100.00
		aes_alert_reset	4.000s	487.613us	1	1	100.00
V2	trigger_clear_test	aes_clear	4.000s	217.700us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	341.645us	1	1	100.00
V2	reset_recovery	aes_alert_reset	4.000s	487.613us	1	1	100.00
V2	stress	aes_stress	2.000s	68.254us	1	1	100.00
V2	sideload	aes_stress	2.000s	68.254us	1	1	100.00
		aes_sideload	3.000s	191.892us	1	1	100.00
V2	deinitialization	aes_deinit	3.000s	163.521us	1	1	100.00
V2	stress_all	aes_stress_all	8.000s	1.079ms	1	1	100.00
V2	alert_test	aes_alert_test	2.000s	57.527us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.000s	132.046us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.000s	132.046us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	86.431us	1	1	100.00
		aes_csr_rw	1.000s	143.741us	1	1	100.00
		aes_csr_aliasing	3.000s	142.045us	1	1	100.00
		aes_same_csr_outstanding	3.000s	159.363us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	86.431us	1	1	100.00
		aes_csr_rw	1.000s	143.741us	1	1	100.00
		aes_csr_aliasing	3.000s	142.045us	1	1	100.00
		aes_same_csr_outstanding	3.000s	159.363us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	5.000s	162.899us	1	1	100.00
V2S	fault_inject	aes_fi	4.000s	440.733us	1	1	100.00
		aes_control_fi	2.000s	56.177us	1	1	100.00
		aes_cipher_fi	2.000s	53.104us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.000s	212.293us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.000s	212.293us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.000s	212.293us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.000s	212.293us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.000s	153.872us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	4.000s	1.556ms	1	1	100.00
		aes_tl_intg_err	2.000s	121.028us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.000s	121.028us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	4.000s	487.613us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.000s	212.293us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	2.000s	82.540us	1	1	100.00
		aes_stress	2.000s	68.254us	1	1	100.00
		aes_alert_reset	4.000s	487.613us	1	1	100.00
		aes_core_fi	3.000s	93.087us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.000s	212.293us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.000s	104.698us	1	1	100.00
		aes_stress	2.000s	68.254us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	2.000s	68.254us	1	1	100.00
		aes_sideload	3.000s	191.892us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.000s	104.698us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.000s	104.698us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.000s	104.698us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.000s	104.698us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.000s	104.698us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	2.000s	68.254us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	2.000s	68.254us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	4.000s	440.733us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	4.000s	440.733us	1	1	100.00
		aes_control_fi	2.000s	56.177us	1	1	100.00
		aes_cipher_fi	2.000s	53.104us	1	1	100.00
		aes_ctr_fi	2.000s	60.581us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	4.000s	440.733us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	4.000s	440.733us	1	1	100.00
		aes_control_fi	2.000s	56.177us	1	1	100.00
		aes_cipher_fi	2.000s	53.104us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	2.000s	53.104us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	4.000s	440.733us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	4.000s	440.733us	1	1	100.00
		aes_control_fi	2.000s	56.177us	1	1	100.00
		aes_ctr_fi	2.000s	60.581us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	4.000s	440.733us	1	1	100.00
		aes_control_fi	2.000s	56.177us	1	1	100.00
		aes_cipher_fi	2.000s	53.104us	1	1	100.00
		aes_ctr_fi	2.000s	60.581us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	4.000s	487.613us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	4.000s	440.733us	1	1	100.00
		aes_control_fi	2.000s	56.177us	1	1	100.00
		aes_cipher_fi	2.000s	53.104us	1	1	100.00
		aes_ctr_fi	2.000s	60.581us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	4.000s	440.733us	1	1	100.00
		aes_control_fi	2.000s	56.177us	1	1	100.00
		aes_cipher_fi	2.000s	53.104us	1	1	100.00
		aes_ctr_fi	2.000s	60.581us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	4.000s	440.733us	1	1	100.00
		aes_control_fi	2.000s	56.177us	1	1	100.00
		aes_ctr_fi	2.000s	60.581us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	4.000s	440.733us	1	1	100.00
		aes_control_fi	2.000s	56.177us	1	1	100.00
		aes_cipher_fi	2.000s	53.104us	1	1	100.00
V2S		TOTAL			11	11	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	16.000s	759.432us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			31	32	96.88

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.2910411958591123152481745555427712137178286266072436380253788985581358909081
      Line 299, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 759431768 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 759431768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---