DMA Simulation Results

Thursday October 23 2025 16:00:55 UTC

GitHub Revision: 1ba76ab

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	4.000s	1.162ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	5.000s	423.128us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	4.000s	2.612ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	36.979us	1	1	100.00
V1	csr_rw	dma_csr_rw	2.000s	71.705us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	7.000s	1.519ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	5.000s	614.560us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	84.282us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	71.705us	1	1	100.00
		dma_csr_aliasing	5.000s	614.560us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	58.000s	4.134ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	1.517m	19.443ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	3.300m	74.626ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	3.300m	74.626ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	1.517m	19.443ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	2.200m	29.758ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	3.300m	74.626ms	1	1	100.00
V2	dma_abort	dma_abort	8.000s	606.120us	1	1	100.00
V2	dma_stress_all	dma_stress_all	3.533m	39.323ms	1	1	100.00
V2	alert_test	dma_alert_test	1.000s	136.515us	1	1	100.00
V2	intr_test	dma_intr_test	1.000s	23.434us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	2.000s	98.257us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	2.000s	98.257us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	36.979us	1	1	100.00
		dma_csr_rw	2.000s	71.705us	1	1	100.00
		dma_csr_aliasing	5.000s	614.560us	1	1	100.00
		dma_same_csr_outstanding	2.000s	96.164us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	36.979us	1	1	100.00
		dma_csr_rw	2.000s	71.705us	1	1	100.00
		dma_csr_aliasing	5.000s	614.560us	1	1	100.00
		dma_same_csr_outstanding	2.000s	96.164us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	14.000s	74.205us	1	1	100.00
		dma_generic_stress	2.200m	29.758ms	1	1	100.00
		dma_handshake_stress	3.300m	74.626ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	8.000s	1.358ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	2.000s	332.184us	1	1	100.00
		dma_sec_cm	2.000s	26.960us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.933m	60.146ms	1	1	100.00
		dma_longer_transfer	3.000s	269.028us	1	1	100.00
		dma_stress_all_with_rand_reset	4.000s	115.024us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.12264773163323983856099662246445698984545605375537630572408357824539518668481
      Line 89, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  115024045ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  115024045ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---