EDN Simulation Results

Thursday October 23 2025 16:00:55 UTC

GitHub Revision: 1ba76ab

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.950s 80.304us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.870s 38.198us 1 1 100.00
V1 csr_rw edn_csr_rw 0.830s 26.203us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.650s 2.121ms 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 0.890s 15.710us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.010s 20.506us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.830s 26.203us 1 1 100.00
edn_csr_aliasing 0.890s 15.710us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.350s 53.145us 1 1 100.00
V2 csrng_commands edn_genbits 1.350s 53.145us 1 1 100.00
V2 genbits edn_genbits 1.350s 53.145us 1 1 100.00
V2 interrupts edn_intr 1.010s 27.353us 1 1 100.00
V2 alerts edn_alert 1.000s 92.567us 1 1 100.00
V2 errs edn_err 0.920s 21.479us 1 1 100.00
V2 disable edn_disable 0.970s 27.686us 1 1 100.00
edn_disable_auto_req_mode 0.860s 72.284us 1 1 100.00
V2 stress_all edn_stress_all 1.180s 62.238us 1 1 100.00
V2 intr_test edn_intr_test 0.830s 17.221us 1 1 100.00
V2 alert_test edn_alert_test 0.930s 16.083us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 1.030s 60.229us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 1.030s 60.229us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.870s 38.198us 1 1 100.00
edn_csr_rw 0.830s 26.203us 1 1 100.00
edn_csr_aliasing 0.890s 15.710us 1 1 100.00
edn_same_csr_outstanding 0.960s 29.451us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.870s 38.198us 1 1 100.00
edn_csr_rw 0.830s 26.203us 1 1 100.00
edn_csr_aliasing 0.890s 15.710us 1 1 100.00
edn_same_csr_outstanding 0.960s 29.451us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 3.910s 1.065ms 1 1 100.00
edn_tl_intg_err 1.300s 75.448us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.920s 15.251us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.000s 92.567us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 3.910s 1.065ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 3.910s 1.065ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 3.910s 1.065ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 3.910s 1.065ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.000s 92.567us 1 1 100.00
edn_sec_cm 3.910s 1.065ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.000s 92.567us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 1.300s 75.448us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets