HMAC Simulation Results

Thursday October 23 2025 16:00:55 UTC

GitHub Revision: 1ba76ab

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 8.540s 483.809us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.940s 27.145us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.960s 36.194us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.640s 1.406ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.100s 508.322us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.970s 102.261us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.960s 36.194us 1 1 100.00
hmac_csr_aliasing 4.100s 508.322us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 9.240s 4.697ms 1 1 100.00
V2 back_pressure hmac_back_pressure 33.170s 872.837us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.010s 175.389us 1 1 100.00
hmac_test_sha384_vectors 18.970s 955.566us 1 1 100.00
hmac_test_sha512_vectors 6.309m 48.770ms 1 1 100.00
hmac_test_hmac256_vectors 5.650s 915.382us 1 1 100.00
hmac_test_hmac384_vectors 8.420s 1.099ms 1 1 100.00
hmac_test_hmac512_vectors 8.160s 245.559us 1 1 100.00
V2 burst_wr hmac_burst_wr 1.890s 74.612us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 10.947m 9.441ms 1 1 100.00
V2 error hmac_error 50.990s 23.717ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.492m 35.180ms 1 1 100.00
V2 save_and_restore hmac_smoke 8.540s 483.809us 1 1 100.00
hmac_long_msg 9.240s 4.697ms 1 1 100.00
hmac_back_pressure 33.170s 872.837us 1 1 100.00
hmac_datapath_stress 10.947m 9.441ms 1 1 100.00
hmac_burst_wr 1.890s 74.612us 1 1 100.00
hmac_stress_all 1.073m 30.300ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 8.540s 483.809us 1 1 100.00
hmac_long_msg 9.240s 4.697ms 1 1 100.00
hmac_back_pressure 33.170s 872.837us 1 1 100.00
hmac_datapath_stress 10.947m 9.441ms 1 1 100.00
hmac_wipe_secret 1.492m 35.180ms 1 1 100.00
hmac_test_sha256_vectors 8.010s 175.389us 1 1 100.00
hmac_test_sha384_vectors 18.970s 955.566us 1 1 100.00
hmac_test_sha512_vectors 6.309m 48.770ms 1 1 100.00
hmac_test_hmac256_vectors 5.650s 915.382us 1 1 100.00
hmac_test_hmac384_vectors 8.420s 1.099ms 1 1 100.00
hmac_test_hmac512_vectors 8.160s 245.559us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 8.540s 483.809us 1 1 100.00
hmac_long_msg 9.240s 4.697ms 1 1 100.00
hmac_back_pressure 33.170s 872.837us 1 1 100.00
hmac_datapath_stress 10.947m 9.441ms 1 1 100.00
hmac_burst_wr 1.890s 74.612us 1 1 100.00
hmac_error 50.990s 23.717ms 1 1 100.00
hmac_wipe_secret 1.492m 35.180ms 1 1 100.00
hmac_test_sha256_vectors 8.010s 175.389us 1 1 100.00
hmac_test_sha384_vectors 18.970s 955.566us 1 1 100.00
hmac_test_sha512_vectors 6.309m 48.770ms 1 1 100.00
hmac_test_hmac256_vectors 5.650s 915.382us 1 1 100.00
hmac_test_hmac384_vectors 8.420s 1.099ms 1 1 100.00
hmac_test_hmac512_vectors 8.160s 245.559us 1 1 100.00
hmac_stress_all 1.073m 30.300ms 1 1 100.00
V2 stress_all hmac_stress_all 1.073m 30.300ms 1 1 100.00
V2 alert_test hmac_alert_test 0.590s 14.081us 1 1 100.00
V2 intr_test hmac_intr_test 0.710s 13.662us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.450s 241.397us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.450s 241.397us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.940s 27.145us 1 1 100.00
hmac_csr_rw 0.960s 36.194us 1 1 100.00
hmac_csr_aliasing 4.100s 508.322us 1 1 100.00
hmac_same_csr_outstanding 1.440s 302.250us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.940s 27.145us 1 1 100.00
hmac_csr_rw 0.960s 36.194us 1 1 100.00
hmac_csr_aliasing 4.100s 508.322us 1 1 100.00
hmac_same_csr_outstanding 1.440s 302.250us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.880s 43.836us 1 1 100.00
hmac_tl_intg_err 3.080s 2.057ms 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.080s 2.057ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 8.540s 483.809us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.260s 433.106us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 31.340s 13.149ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 0.690s 39.035us 1 1 100.00
TOTAL 28 28 100.00