I2C Simulation Results

Thursday October 23 2025 16:00:55 UTC

GitHub Revision: 1ba76ab

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	30.190s	9.502ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	10.430s	2.935ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.940s	72.806us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.810s	31.471us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.190s	245.970us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.810s	161.047us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.120s	37.828us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.810s	31.471us	1	1	100.00
		i2c_csr_aliasing	1.810s	161.047us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.880s	23.716us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	11.588m	30.073ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	5.620s	444.043us	1	1	100.00
V2	host_override	i2c_host_override	0.960s	215.360us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	42.640s	10.515ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.046m	6.184ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.230s	254.409us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.340s	1.984ms	1	1	100.00
		i2c_host_fifo_reset_rx	10.640s	784.882us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	36.560s	2.593ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	22.000s	2.906ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.090s	61.402us	0	1	0.00
V2	target_glitch	i2c_target_glitch	3.570s	1.986ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	1.068m	57.416ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.840s	2.622ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	20.740s	1.464ms	1	1	100.00
		i2c_target_intr_smoke	5.010s	2.552ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.060s	289.598us	1	1	100.00
		i2c_target_fifo_reset_tx	0.910s	739.505us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	7.592m	67.592ms	1	1	100.00
		i2c_target_stress_rd	20.740s	1.464ms	1	1	100.00
		i2c_target_intr_stress_wr	19.580s	16.535ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.060s	1.257ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	26.330s	3.579ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.680s	1.915ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	10.710s	10.346ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.300s	459.805us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.290s	265.508us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	5.620s	444.043us	1	1	100.00
		i2c_host_perf_precise	3.230s	507.094us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	22.000s	2.906ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.410s	97.376us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.290s	2.212ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.960s	880.442us	1	1	100.00
		i2c_target_nack_txstretch	1.370s	328.523us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	7.070s	1.264ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.530s	413.519us	1	1	100.00
V2	alert_test	i2c_alert_test	0.720s	14.650us	1	1	100.00
V2	intr_test	i2c_intr_test	0.870s	17.204us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.990s	532.181us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.990s	532.181us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.940s	72.806us	1	1	100.00
		i2c_csr_rw	0.810s	31.471us	1	1	100.00
		i2c_csr_aliasing	1.810s	161.047us	1	1	100.00
		i2c_same_csr_outstanding	0.900s	41.045us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.940s	72.806us	1	1	100.00
		i2c_csr_rw	0.810s	31.471us	1	1	100.00
		i2c_csr_aliasing	1.810s	161.047us	1	1	100.00
		i2c_same_csr_outstanding	0.900s	41.045us	1	1	100.00
V2		TOTAL			32	38	84.21
V2S	tl_intg_err	i2c_tl_intg_err	2.150s	466.167us	1	1	100.00
		i2c_sec_cm	1.020s	74.807us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.150s	466.167us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	38.620s	4.279ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.180s	125.381us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	1.720s	188.073us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			41	50	82.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.90885933649883193128734185650604494756195010445347769872774474257044300974191
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  23716244 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  23716244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.94043205324857918120704034793862843527846471313400014453298276363119145342778
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 188072709 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 188072709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.79099852644877743653083085958390326889446202720342110412922508337390855294309
      Line 159, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 30072793988 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @14491043
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.98172422383698261226648007656780626749024686925980620239357101628165195249217
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 1986250273 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 1986250273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.63908803050933716037400299783021008156510875910719267570918997003635314699865
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 125381486 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 125381486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.31428344080309956695707029253643102075503036544172455876201878823574177206111
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10346429746 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10346429746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.76586647234387791438242946771428714104665400926898171284723235836665810786924
      Line 94, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4278653501 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4278653501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.105831468636882111659559306238539978459088953162412914653895000557059358953249
      Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  61402411 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
        ---------------------------------------------------
        Name            Type                Size  Value
        ---------------------------------------------------
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.65810708449288408364305513865531936448924002104646635030461744929576787585544
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 328522780 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 328522780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---