KMAC/UNMASKED Simulation Results

Thursday October 23 2025 16:00:55 UTC

GitHub Revision: 1ba76ab

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	17.280s	513.936us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.920s	54.958us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.850s	19.229us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.290s	978.898us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	2.790s	70.693us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.460s	53.661us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.850s	19.229us	1	1	100.00
		kmac_csr_aliasing	2.790s	70.693us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.680s	13.683us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	0.990s	33.283us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	18.178m	64.858ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.487m	16.207ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	27.490m	179.455ms	1	1	100.00
		kmac_test_vectors_sha3_256	26.460s	6.592ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.750s	1.654ms	1	1	100.00
		kmac_test_vectors_sha3_512	8.990s	267.492us	1	1	100.00
		kmac_test_vectors_shake_128	32.614m	388.257ms	1	1	100.00
		kmac_test_vectors_shake_256	25.149m	79.507ms	1	1	100.00
		kmac_test_vectors_kmac	1.710s	266.703us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.430s	117.738us	1	1	100.00
V2	sideload	kmac_sideload	5.107m	87.265ms	1	1	100.00
V2	app	kmac_app	1.896m	7.456ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.183m	10.939ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.454m	83.747ms	1	1	100.00
V2	error	kmac_error	1.190m	18.970ms	1	1	100.00
V2	key_error	kmac_key_error	2.610s	632.012us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	21.430s	10.149ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	16.750s	720.733us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	4.950s	1.016ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	27.430s	5.051ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.020s	52.105us	1	1	100.00
V2	stress_all	kmac_stress_all	23.137m	81.407ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.640s	14.251us	1	1	100.00
V2	alert_test	kmac_alert_test	0.660s	22.347us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.480s	257.532us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.480s	257.532us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.920s	54.958us	1	1	100.00
		kmac_csr_rw	0.850s	19.229us	1	1	100.00
		kmac_csr_aliasing	2.790s	70.693us	1	1	100.00
		kmac_same_csr_outstanding	1.850s	104.570us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.920s	54.958us	1	1	100.00
		kmac_csr_rw	0.850s	19.229us	1	1	100.00
		kmac_csr_aliasing	2.790s	70.693us	1	1	100.00
		kmac_same_csr_outstanding	1.850s	104.570us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.430s	262.071us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.430s	262.071us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.430s	262.071us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.430s	262.071us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.870s	158.695us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	23.680s	9.417ms	1	1	100.00
		kmac_tl_intg_err	2.900s	385.918us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.900s	385.918us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.020s	52.105us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	17.280s	513.936us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.107m	87.265ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.430s	262.071us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	23.680s	9.417ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	23.680s	9.417ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	23.680s	9.417ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	17.280s	513.936us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.020s	52.105us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	23.680s	9.417ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.031m	19.602ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	17.280s	513.936us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.213m	42.429ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.27896668600942166174392537245077759268991050585445031749469710629856638148385
      Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10149315472 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x29dc3000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
        UVM_INFO @ 10149315472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---