1ba76ab| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 46.000s | 4.233ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 2.000s | 162.816us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 2.000s | 28.019us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 3.000s | 352.044us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 1.000s | 38.170us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 2.000s | 76.547us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 2.000s | 28.019us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 1.000s | 38.170us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | mbx_stress | mbx_stress | 10.000s | 2.773ms | 0 | 1 | 0.00 |
| V2 | mbx_max_activity | mbx_stress_zero_delays | 2.000s | 26.045us | 0 | 1 | 0.00 |
| V2 | mbx_imbx_oob | mbx_imbx_oob | 23.000s | 10.154ms | 0 | 1 | 0.00 |
| V2 | mbx_doe_intr_msg | mbx_doe_intr_msg | 10.000s | 2.720ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 1.000s | 14.833us | 1 | 1 | 100.00 |
| V2 | intr_test | mbx_intr_test | 1.000s | 23.008us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 3.000s | 399.311us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 3.000s | 399.311us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 2.000s | 162.816us | 1 | 1 | 100.00 |
| mbx_csr_rw | 2.000s | 28.019us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 1.000s | 38.170us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 1.000s | 20.546us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 2.000s | 162.816us | 1 | 1 | 100.00 |
| mbx_csr_rw | 2.000s | 28.019us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 1.000s | 38.170us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 1.000s | 20.546us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 8 | 62.50 | |||
| V2S | tl_intg_err | mbx_tl_intg_err | 2.000s | 273.723us | 1 | 1 | 100.00 |
| mbx_sec_cm | 2.000s | 21.879us | 1 | 1 | 100.00 | ||
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| TOTAL | 13 | 16 | 81.25 |
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 2 failures:
Test mbx_stress_zero_delays has 1 failures.
0.mbx_stress_zero_delays.97370440777870590836807891774096080939006526428750399583240819534599286636677
Line 86, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest/run.log
UVM_ERROR @ 26045134 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 26045134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_imbx_oob has 1 failures.
0.mbx_imbx_oob.82628845448906544762738862326355501795508414155644200612808278195459976977406
Line 144, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_imbx_oob/latest/run.log
UVM_ERROR @ 10153772776 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 10153772776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched has 1 failures:
0.mbx_stress.62319154136011582036544850846219345678957197601739769962559557107254265025163
Line 377, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log
UVM_ERROR @ 2773468986 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (3798920678 [0xe26eede6] vs 0 [0x0]) RDATA read data mismatched
UVM_INFO @ 2773468986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---