OTBN Simulation Results

Thursday October 23 2025 16:00:55 UTC

GitHub Revision: 1ba76ab

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 10.000s 73.398us 0 1 0.00
V1 single_binary otbn_single 7.000s 65.431us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 3.000s 87.786us 1 1 100.00
V1 csr_rw otbn_csr_rw 3.000s 15.629us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 5.000s 140.670us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 3.000s 33.542us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 7.000s 308.988us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 3.000s 15.629us 1 1 100.00
otbn_csr_aliasing 3.000s 33.542us 1 1 100.00
V1 mem_walk otbn_mem_walk 38.000s 1.885ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 15.000s 479.114us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 30.000s 355.426us 0 1 0.00
V2 multi_error otbn_multi_err 46.000s 275.701us 0 1 0.00
V2 back_to_back otbn_multi 25.000s 89.403us 0 1 0.00
V2 stress_all otbn_stress_all 33.000s 145.435us 0 1 0.00
V2 lc_escalation otbn_escalate 7.000s 46.176us 0 1 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 7.000s 17.973us 0 1 0.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 31.000s 147.476us 0 1 0.00
V2 alert_test otbn_alert_test 5.000s 25.791us 1 1 100.00
V2 intr_test otbn_intr_test 4.000s 22.484us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 6.000s 119.071us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 6.000s 119.071us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 3.000s 87.786us 1 1 100.00
otbn_csr_rw 3.000s 15.629us 1 1 100.00
otbn_csr_aliasing 3.000s 33.542us 1 1 100.00
otbn_same_csr_outstanding 4.000s 18.347us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 3.000s 87.786us 1 1 100.00
otbn_csr_rw 3.000s 15.629us 1 1 100.00
otbn_csr_aliasing 3.000s 33.542us 1 1 100.00
otbn_same_csr_outstanding 4.000s 18.347us 1 1 100.00
V2 TOTAL 4 11 36.36
V2S mem_integrity otbn_imem_err 8.000s 25.117us 0 1 0.00
otbn_dmem_err 9.000s 82.539us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 9.000s 104.020us 0 1 0.00
otbn_controller_ispr_rdata_err 12.000s 156.315us 0 1 0.00
otbn_mac_bignum_acc_err 6.000s 588.895us 0 1 0.00
otbn_urnd_err 4.000s 24.334us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 5.000s 28.315us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 5.000s 21.486us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 5.000s 26.331us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 7.000s 43.017us 0 1 0.00
otbn_tl_intg_err 14.000s 103.475us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 11.000s 95.776us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 7.000s 43.017us 0 1 0.00
V2S prim_count_check otbn_sec_cm 7.000s 43.017us 0 1 0.00
V2S sec_cm_mem_scramble otbn_smoke 10.000s 73.398us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 9.000s 82.539us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 8.000s 25.117us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 14.000s 103.475us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 7.000s 46.176us 0 1 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 8.000s 25.117us 0 1 0.00
otbn_dmem_err 9.000s 82.539us 0 1 0.00
otbn_zero_state_err_urnd 7.000s 17.973us 0 1 0.00
otbn_illegal_mem_acc 5.000s 28.315us 1 1 100.00
otbn_sec_cm 7.000s 43.017us 0 1 0.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 7.000s 43.017us 0 1 0.00
V2S sec_cm_scramble_key_sideload otbn_single 7.000s 65.431us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 8.000s 25.117us 0 1 0.00
otbn_dmem_err 9.000s 82.539us 0 1 0.00
otbn_zero_state_err_urnd 7.000s 17.973us 0 1 0.00
otbn_illegal_mem_acc 5.000s 28.315us 1 1 100.00
otbn_sec_cm 7.000s 43.017us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 7.000s 43.017us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 7.000s 46.176us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 8.000s 25.117us 0 1 0.00
otbn_dmem_err 9.000s 82.539us 0 1 0.00
otbn_zero_state_err_urnd 7.000s 17.973us 0 1 0.00
otbn_illegal_mem_acc 5.000s 28.315us 1 1 100.00
otbn_sec_cm 7.000s 43.017us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 7.000s 43.017us 0 1 0.00
V2S sec_cm_data_reg_sw_sca otbn_single 7.000s 65.431us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 7.000s 27.765us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 4.000s 41.023us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 34.000s 298.897us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 34.000s 298.897us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 6.000s 51.231us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 7.000s 43.017us 0 1 0.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 7.000s 43.017us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 6.000s 214.255us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 7.000s 43.017us 0 1 0.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 7.000s 43.017us 0 1 0.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 9.000s 36.175us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 9.000s 36.175us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 10.000s 54.341us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 7.000s 65.431us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 7.000s 65.431us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 7.000s 65.431us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 25.000s 89.403us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 7.000s 65.431us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 7.000s 65.431us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 7.000s 222.154us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 7.000s 65.431us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 7.000s 43.017us 0 1 0.00
V2S TOTAL 8 20 40.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 4.067m 2.553ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 19 41 46.34

Failure Buckets