ROM_CTRL/32KB Simulation Results

Thursday October 23 2025 16:00:55 UTC

GitHub Revision: 1ba76ab

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.750s 1.514ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.080s 176.766us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 3.480s 591.790us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 3.810s 818.520us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 3.450s 385.920us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.370s 591.330us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 3.480s 591.790us 1 1 100.00
rom_ctrl_csr_aliasing 3.450s 385.920us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.560s 814.042us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.870s 728.971us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.260s 173.434us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 16.190s 3.111ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.730s 970.005us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.680s 297.864us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.670s 288.077us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.670s 288.077us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.080s 176.766us 1 1 100.00
rom_ctrl_csr_rw 3.480s 591.790us 1 1 100.00
rom_ctrl_csr_aliasing 3.450s 385.920us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.720s 130.702us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.080s 176.766us 1 1 100.00
rom_ctrl_csr_rw 3.480s 591.790us 1 1 100.00
rom_ctrl_csr_aliasing 3.450s 385.920us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.720s 130.702us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 59.950s 1.788ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 19.750s 3.374ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.219m 3.537ms 1 1 100.00
rom_ctrl_tl_intg_err 46.840s 453.339us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.219m 3.537ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.219m 3.537ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 59.950s 1.788ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 59.950s 1.788ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 59.950s 1.788ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 59.950s 1.788ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 59.950s 1.788ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.219m 3.537ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.219m 3.537ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.750s 1.514ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.750s 1.514ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.750s 1.514ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 46.840s 453.339us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 59.950s 1.788ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.730s 970.005us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 59.950s 1.788ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 59.950s 1.788ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 59.950s 1.788ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 19.750s 3.374ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.219m 3.537ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.568m 17.669ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00