RV_TIMER Simulation Results

Thursday October 23 2025 16:00:55 UTC

GitHub Revision: 1ba76ab

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.760s	138.567us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.650s	32.458us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.680s	32.633us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.370s	174.261us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.900s	109.996us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.160s	77.173us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.680s	32.633us	1	1	100.00
		rv_timer_csr_aliasing	0.900s	109.996us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.700s	398.073us	0	1	0.00
V2	disabled	rv_timer_disabled	2.170s	1.372ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	8.512m	423.933ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	8.512m	423.933ms	1	1	100.00
V2	stress	rv_timer_stress_all	1.110s	936.534us	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.660s	28.535us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.680s	14.786us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.350s	640.762us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.350s	640.762us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.650s	32.458us	1	1	100.00
		rv_timer_csr_rw	0.680s	32.633us	1	1	100.00
		rv_timer_csr_aliasing	0.900s	109.996us	1	1	100.00
		rv_timer_same_csr_outstanding	0.670s	61.839us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.650s	32.458us	1	1	100.00
		rv_timer_csr_rw	0.680s	32.633us	1	1	100.00
		rv_timer_csr_aliasing	0.900s	109.996us	1	1	100.00
		rv_timer_same_csr_outstanding	0.670s	61.839us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.900s	98.101us	1	1	100.00
		rv_timer_tl_intg_err	1.240s	109.447us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.240s	109.447us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.920s	56.750us	0	1	0.00
V3	max_value	rv_timer_max	1.910s	703.215us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	32.040s	5.874ms	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.96018623052576594928388970970346953140188566384217982352891686597947719915364
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @  56750297 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x96b01704) == 0x1
        UVM_INFO @  56750297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.92315456467122179093966029241541874162038247663432976550481897615600111123847
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 398073114 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x7a33d104) == 0x1
        UVM_INFO @ 398073114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:365) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.32704405832513682683384748558448092782704484005386468431560549724264522386582
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 703214638 ps: (rv_timer_scoreboard.sv:365) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
        UVM_INFO @ 703214638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---