SPI_DEVICE/1R1W Simulation Results

Thursday October 23 2025 16:00:55 UTC

GitHub Revision: 1ba76ab

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	14.380s	11.310ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.010s	36.365us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.340s	89.630us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.010s	1.257ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.390s	208.078us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.680s	61.310us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.340s	89.630us	1	1	100.00
		spi_device_csr_aliasing	10.390s	208.078us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	26.102us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.820s	86.059us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.960s	17.517us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.860s	1.802us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.870s	3.863us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.100s	61.598us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.100s	61.598us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.320s	1.919ms	1	1	100.00
		spi_device_tpm_sts_read	1.130s	325.380us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	21.370s	4.263ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	8.940s	15.470ms	1	1	100.00
		spi_device_flash_all	3.024m	148.440ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.860s	1.142ms	1	1	100.00
		spi_device_flash_all	3.024m	148.440ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.860s	1.142ms	1	1	100.00
		spi_device_flash_all	3.024m	148.440ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	3.024m	148.440ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.580s	62.816us	1	1	100.00
		spi_device_flash_all	3.024m	148.440ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.580s	62.816us	1	1	100.00
		spi_device_flash_all	3.024m	148.440ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.580s	62.816us	1	1	100.00
		spi_device_flash_all	3.024m	148.440ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.580s	62.816us	1	1	100.00
		spi_device_flash_all	3.024m	148.440ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.580s	62.816us	1	1	100.00
		spi_device_flash_all	3.024m	148.440ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	7.270s	1.281ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	28.400s	21.446ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	28.400s	21.446ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	28.400s	21.446ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.840s	532.676us	1	1	100.00
		spi_device_read_buffer_direct	3.120s	1.215ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	28.400s	21.446ms	1	1	100.00
		spi_device_flash_all	3.024m	148.440ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	3.024m	148.440ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	3.024m	148.440ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.910s	341.317us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.910s	341.317us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.380s	11.310ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	35.050s	47.725ms	1	1	100.00
V2	stress_all	spi_device_stress_all	20.030s	2.098ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.910s	12.614us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.760s	13.832us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.070s	522.032us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.070s	522.032us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.010s	36.365us	1	1	100.00
		spi_device_csr_rw	1.340s	89.630us	1	1	100.00
		spi_device_csr_aliasing	10.390s	208.078us	1	1	100.00
		spi_device_same_csr_outstanding	3.020s	310.074us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.010s	36.365us	1	1	100.00
		spi_device_csr_rw	1.340s	89.630us	1	1	100.00
		spi_device_csr_aliasing	10.390s	208.078us	1	1	100.00
		spi_device_same_csr_outstanding	3.020s	310.074us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.100s	75.684us	1	1	100.00
		spi_device_tl_intg_err	4.940s	119.343us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	4.940s	119.343us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.016m	97.248ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.38158372066072368124332160123592859238993844463495106564156101649724626248809
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1291876 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[35])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1291876 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1291876 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[931])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.111578726076395313599126831035275251428970672607723281784615025858302618660426
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1402834 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfdf17b [111111011111000101111011] vs 0x0 [0])
        UVM_ERROR @   1410834 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x11f90a [100011111100100001010] vs 0x0 [0])
        UVM_ERROR @   1459834 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x709a97 [11100001001101010010111] vs 0x0 [0])
        UVM_ERROR @   1493834 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xba992 [10111010100110010010] vs 0x0 [0])
        UVM_ERROR @   1573834 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x839be5 [100000111001101111100101] vs 0x0 [0])