SPI_HOST Simulation Results

Thursday October 23 2025 16:00:55 UTC

GitHub Revision: 1ba76ab

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	25.000s	540.927us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	24.344us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	29.575us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	87.527us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	58.879us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	36.692us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	29.575us	1	1	100.00
		spi_host_csr_aliasing	2.000s	58.879us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	15.461us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	64.504us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	7.000s	37.187us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	11.000s	251.918us	1	1	100.00
		spi_host_error_cmd	7.000s	83.483us	1	1	100.00
		spi_host_event	12.000s	1.529ms	1	1	100.00
V2	clock_rate	spi_host_speed	9.000s	96.548us	1	1	100.00
V2	speed	spi_host_speed	9.000s	96.548us	1	1	100.00
V2	chip_select_timing	spi_host_speed	9.000s	96.548us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	36.000s	1.568ms	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	6.000s	104.076us	1	1	100.00
V2	cpol_cpha	spi_host_speed	9.000s	96.548us	1	1	100.00
V2	full_cycle	spi_host_speed	9.000s	96.548us	1	1	100.00
V2	duplex	spi_host_smoke	25.000s	540.927us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	25.000s	540.927us	1	1	100.00
V2	stress_all	spi_host_stress_all	6.000s	66.972us	1	1	100.00
V2	spien	spi_host_spien	4.000s	939.601us	1	1	100.00
V2	stall	spi_host_status_stall	14.000s	594.821us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	8.000s	453.158us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	11.000s	251.918us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	32.577us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	18.295us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	3.000s	95.989us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	3.000s	95.989us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	24.344us	1	1	100.00
		spi_host_csr_rw	1.000s	29.575us	1	1	100.00
		spi_host_csr_aliasing	2.000s	58.879us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	59.877us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	24.344us	1	1	100.00
		spi_host_csr_rw	1.000s	29.575us	1	1	100.00
		spi_host_csr_aliasing	2.000s	58.879us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	59.877us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	60.778us	1	1	100.00
		spi_host_sec_cm	1.000s	232.049us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	60.778us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	12.083m	57.406ms	1	1	100.00
		TOTAL			26	26	100.00