SRAM_CTRL/MAIN Simulation Results

Thursday October 23 2025 16:00:55 UTC

GitHub Revision: 1ba76ab

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	13.210s	1.899ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.820s	26.138us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.880s	13.464us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.040s	34.895us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.900s	19.483us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.540s	1.457ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.880s	13.464us	1	1	100.00
		sram_ctrl_csr_aliasing	0.900s	19.483us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.958m	98.775ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.974m	5.622ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.506m	69.368ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.018m	7.272ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	15.644m	263.944ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.457m	14.026ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.034m	32.436ms	1	1	100.00
V2	executable	sram_ctrl_executable	10.314m	60.317ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	7.260s	894.040us	1	1	100.00
		sram_ctrl_partial_access_b2b	2.819m	9.871ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	13.080s	718.568us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	3.920s	1.246ms	1	1	100.00
		sram_ctrl_throughput_w_readback	13.460s	3.130ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.043m	8.233ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.190s	363.055us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	43.881m	643.288ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.980s	37.052us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.770s	38.937us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.770s	38.937us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.820s	26.138us	1	1	100.00
		sram_ctrl_csr_rw	0.880s	13.464us	1	1	100.00
		sram_ctrl_csr_aliasing	0.900s	19.483us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.670s	46.658us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.820s	26.138us	1	1	100.00
		sram_ctrl_csr_rw	0.880s	13.464us	1	1	100.00
		sram_ctrl_csr_aliasing	0.900s	19.483us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.670s	46.658us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	34.700s	100.664ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.780s	7.471us	0	1	0.00
		sram_ctrl_tl_intg_err	1.920s	162.662us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.780s	7.471us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.920s	162.662us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.043m	8.233ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.043m	8.233ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.880s	13.464us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	10.314m	60.317ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	10.314m	60.317ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	10.314m	60.317ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.034m	32.436ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	9.080s	2.094ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	34.700s	100.664ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	3.690s	693.669us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	13.210s	1.899ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	13.210s	1.899ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	10.314m	60.317ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.780s	7.471us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.034m	32.436ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.780s	7.471us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.780s	7.471us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	13.210s	1.899ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.780s	7.471us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	9.060s	298.450us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.57964642968919616578428005847650905699306610653720882717106372153248643882702
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 693668844 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3f) != exp (0x6d)
        UVM_INFO @ 693668844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.71824391039243365904181984930719100461926911429968048729019307790589031781120
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7470849 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7470849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---