UART Simulation Results

Thursday October 23 2025 16:00:55 UTC

GitHub Revision: 1ba76ab

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.530s	498.249us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.610s	45.406us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.660s	15.130us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.940s	252.913us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.860s	64.718us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.140s	246.849us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.660s	15.130us	1	1	100.00
		uart_csr_aliasing	0.860s	64.718us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.885m	84.804ms	1	1	100.00
V2	parity	uart_smoke	2.530s	498.249us	1	1	100.00
		uart_tx_rx	1.885m	84.804ms	1	1	100.00
V2	parity_error	uart_intr	1.388m	71.155ms	1	1	100.00
		uart_rx_parity_err	29.260s	54.054ms	1	1	100.00
V2	watermark	uart_tx_rx	1.885m	84.804ms	1	1	100.00
		uart_intr	1.388m	71.155ms	1	1	100.00
V2	fifo_full	uart_fifo_full	43.210s	30.518ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.024m	124.636ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.696m	70.608ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.388m	71.155ms	1	1	100.00
V2	rx_break_err	uart_intr	1.388m	71.155ms	1	1	100.00
V2	rx_timeout	uart_intr	1.388m	71.155ms	1	1	100.00
V2	perf	uart_perf	2.274m	8.143ms	1	1	100.00
V2	sys_loopback	uart_loopback	11.450s	9.132ms	1	1	100.00
V2	line_loopback	uart_loopback	11.450s	9.132ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	17.130s	14.474ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.980s	3.618ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.320s	1.491ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	20.510s	6.598ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.525m	59.806ms	1	1	100.00
V2	stress_all	uart_stress_all	3.286m	149.497ms	1	1	100.00
V2	alert_test	uart_alert_test	0.830s	39.206us	1	1	100.00
V2	intr_test	uart_intr_test	0.780s	15.695us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.770s	35.450us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.770s	35.450us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.610s	45.406us	1	1	100.00
		uart_csr_rw	0.660s	15.130us	1	1	100.00
		uart_csr_aliasing	0.860s	64.718us	1	1	100.00
		uart_same_csr_outstanding	0.760s	38.356us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.610s	45.406us	1	1	100.00
		uart_csr_rw	0.660s	15.130us	1	1	100.00
		uart_csr_aliasing	0.860s	64.718us	1	1	100.00
		uart_same_csr_outstanding	0.760s	38.356us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.090s	921.865us	1	1	100.00
		uart_tl_intg_err	1.170s	95.458us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.170s	95.458us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	17.750s	7.908ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.7177954548407249908657926380960828696481794436189839170335733944715001722003
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 4904450841 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 4904450841 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 6002417901 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 6002417901 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 7044134017 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (66 [0x42] vs 126 [0x7e]) reg name: uart_reg_block.rdata
      

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 0.uart_stress_all_with_rand_reset.36807495064998931903602419710796428751694047792577887249748700242268774047910
      Line 151, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7850254955 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 7874553574 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 5/5
        UVM_INFO @ 7874713574 ps: (cip_base_vseq.sv:1166) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 5/5