CHIP Simulation Results

Thursday October 23 2025 16:00:55 UTC

GitHub Revision: `1ba76ab`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.355m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.355m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	12.114s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	12.190s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	14.306s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.464m	5.085ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.464m	5.085ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.464m	5.085ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	33.640s	10.220us	0	1	0.00
		chip_sw_example_manufacturer	2.609m		0	1	0.00
		chip_sw_example_concurrency	4.305m	5.815ms	1	1	100.00
		chip_sw_uart_smoketest_signed	11.500s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	14.830s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	15.350s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	15.350s		0	1	0.00
V1	xbar_smoke	xbar_smoke	18.310s	57.401us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	56.269s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	9.646m	8.637ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.670m	4.228ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	12.625s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	12.576s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	14.204s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	12.626s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	2.830s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.830s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.916m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.922m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.799m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.799m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.353m	3.640ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.006m	4.370ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.935m	15.271ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.903s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	13.330s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	13.992m	15.994ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	7.088m	6.654ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	23.623m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	23.623m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	13.366s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.653m	3.979ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.653m	3.979ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.896m	18.018ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.114m	5.731ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.946m	6.506ms	1	1	100.00
		chip_sw_aes_idle	3.800m	4.199ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.854m	3.253ms	1	1	100.00
		chip_sw_kmac_idle	3.268m	3.512ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	14.035m	12.018ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	14.472m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	14.657m	12.011ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	13.037m	12.027ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	14.490s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.590s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.423s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.765s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.295s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.083s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.773s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	14.490s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.590s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.423s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.765s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.295s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.083s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.773s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	13.279s		0	1	0.00
		chip_sw_aes_enc_jitter_en	35.960s	10.160us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	53.060s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	37.860s	10.160us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	37.340s	10.160us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.049s		0	1	0.00
		chip_sw_clkmgr_jitter	4.344m	4.285ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.473m	3.299ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.678s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	47.210s	10.180us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	39.940s	10.180us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	37.650s	10.160us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	38.700s	10.400us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	35.830s	10.320us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.208s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	13.812s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.456s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.211s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	21.187m	17.396ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	12.993m	16.426ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.653m	3.979ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	19.234s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	12.993m	16.426ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	15.155s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	12.914s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	11.215s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	12.928s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	18.055s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	21.187m	17.396ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.935m	15.271ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	25.918m	20.018ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.912m	8.253ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	9.653m	10.452ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.114m	4.446ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	21.187m	17.396ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	12.747s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	16.945s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	21.187m	17.396ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	14.571s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	9.653m	10.452ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	14.307s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.646s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	14.648s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.425s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	16.867s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	14.716s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	16.945s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	12.831s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.077s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.831s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.831s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.831s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.988m	8.704ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	16.010s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	15.639s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.082s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.528s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.831s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.959m	6.627ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.922m	10.140ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	13.840s		0	1	0.00
		chip_prim_tl_access	25.831m	37.061ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	14.490s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.590s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.423s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.765s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.295s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.083s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.773s		0	1	0.00
		chip_rv_dm_lc_disabled	13.992m	15.994ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.374m	4.008ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	35.960s	10.160us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.551m	5.443ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.800m	4.199ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.492m	4.282ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	53.060s	10.240us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.854m	3.253ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.993m	4.831ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.545m	4.964ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	37.340s	10.160us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.959m	6.627ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.831s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	32.010s	10.120us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.121m	4.154ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.268m	3.512ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.276s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.276s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.241s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.754m	4.924ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	14.302s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.959m	6.627ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	37.860s	10.160us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	12.921s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	13.279s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.946m	6.506ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.946m	6.506ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.946m	6.506ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.558m	4.667ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.922m	10.140ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.922m	10.140ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	9.153m	6.753ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.049s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.840s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	21.187m	17.396ms	1	1	100.00
		chip_sw_data_integrity_escalation	1.799m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.831s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.558m	4.667ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.959m	6.627ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.153m	6.753ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.217m	5.449ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.558m	4.667ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.959m	6.627ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.153m	6.753ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.217m	5.449ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.831s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.187s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.077s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	16.010s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	15.639s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.082s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.528s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.831s		0	1	0.00
		chip_prim_tl_access	25.831m	37.061ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	25.831m	37.061ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	11.921s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.244s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	13.812s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	13.279s		0	1	0.00
		chip_sw_aes_enc_jitter_en	35.960s	10.160us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	53.060s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	37.860s	10.160us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	37.340s	10.160us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.049s		0	1	0.00
		chip_sw_clkmgr_jitter	4.344m	4.285ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.382m	6.894ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.382m	6.894ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.680m	5.386ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.798m	4.548ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.428m	3.745ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.419m	5.299ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.678m	5.133ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.928m	4.190ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.217m	5.449ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	25.918m	20.018ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	25.918m	20.018ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.728m	4.334ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.931m	3.617ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.846m	4.718ms	1	1	100.00
		chip_sw_csrng_smoketest	2.959m	3.652ms	1	1	100.00
		chip_sw_gpio_smoketest	3.984m	3.898ms	1	1	100.00
		chip_sw_hmac_smoketest	4.243m	5.458ms	1	1	100.00
		chip_sw_kmac_smoketest	4.187m	3.890ms	1	1	100.00
		chip_sw_otbn_smoketest	4.345m	5.025ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.847m	4.408ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.753m	3.876ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.820m	4.527ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.091m	4.755ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.357m	4.700ms	1	1	100.00
		chip_sw_uart_smoketest	3.441m	3.539ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	23.057s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	11.500s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	56.269s		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.607s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.635m	5.940ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.609m	5.298ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.472m	5.362ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	46.307m	60.000ms	0	1	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	11.917s		0	1	0.00
		chip_rv_dm_lc_disabled	13.992m	15.994ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	13.015s		0	1	0.00
		chip_sw_lc_walkthrough_prod	14.322s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	12.855s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.279s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	11.917s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	13.446s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	11.304s		0	1	0.00
		rom_volatile_raw_unlock	11.814s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.967s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	14.480s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	32.690s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.378m	3.256ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.378m	3.256ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	15.350s		0	1	0.00
		chip_same_csr_outstanding	14.060s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	15.350s		0	1	0.00
		chip_same_csr_outstanding	14.060s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	25.670s	22.219us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.220s	11.839us	1	1	100.00
		xbar_smoke_large_delays	4.434m	2.250ms	1	1	100.00
		xbar_smoke_slow_rsp	5.946m	2.131ms	1	1	100.00
		xbar_random_zero_delays	1.276m	67.186us	1	1	100.00
		xbar_random_large_delays	14.040m	6.955ms	1	1	100.00
		xbar_random_slow_rsp	29.924m	11.044ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	11.190s	16.283us	1	1	100.00
		xbar_error_and_unmapped_addr	38.650s	27.801us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.546m	221.717us	1	1	100.00
		xbar_error_and_unmapped_addr	38.650s	27.801us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.319m	120.082us	1	1	100.00
		xbar_access_same_device_slow_rsp	44.709m	17.050ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.432m	253.423us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	12.952m	2.032ms	1	1	100.00
		xbar_stress_all_with_error	20.712m	3.315ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	6.536m	272.683us	1	1	100.00
		xbar_stress_all_with_reset_error	18.032m	1.923ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	14.128s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	13.010s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.241s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.856s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.868s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.274s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12.749s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.374s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.043s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.963s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.372s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.503s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	14.463s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	48.329s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.037m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	54.138s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	50.650s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	48.411s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	41.164s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	37.640s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	37.400s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	43.089s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	39.315s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	37.290s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	37.420s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	32.178s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	29.560s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	30.647s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	14.337s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	13.511s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.907s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	15.542s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	14.275s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	13.133s		0	1	0.00
		rom_e2e_asm_init_dev	12.126s		0	1	0.00
		rom_e2e_asm_init_prod	12.973s		0	1	0.00
		rom_e2e_asm_init_prod_end	12.894s		0	1	0.00
		rom_e2e_asm_init_rma	12.434s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	12.634s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.576s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.753s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	13.458s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.461m	3.458ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.075m	4.838ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.503s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.830s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.319s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	13.586s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	21.187m	17.396ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	16.322s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.739m	5.444ms	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	12.372s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.130s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.503s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.830s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.319s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.368s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.076s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.341s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	14.119s		0	1	0.00
V3		TOTAL			0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	20.487m	13.969ms	1	1	100.00
		chip_sw_entropy_src_kat_test	3.950m	4.993ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	5.337m	5.223ms	1	1	100.00
		chip_plic_all_irqs_0	10.395m	7.470ms	1	1	100.00
		chip_plic_all_irqs_10	10.738m	6.240ms	1	1	100.00
		chip_sw_dma_inline_hashing	5.678m	5.234ms	1	1	100.00
		chip_sw_dma_abort	4.089m	4.757ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.680s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	12.121s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.571s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	12.124s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	12.179s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.368s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.368s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	12.155s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	12.263s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	13.699s		0	1	0.00
		chip_sw_entropy_src_smoketest	4.597m	5.687ms	1	1	100.00
		chip_sw_mbx_smoketest	4.071m	4.711ms	1	1	100.00
		TOTAL			78	250	31.20

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.80999628509246178599915089625537646593489703967635247657105787316857947970444
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 144.639s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.38515129607656431015983933035840298052016881397607479630577223631115106900601
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 96.990s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.103001079899666313977708623972901509316094845795469265363801092186983032750831
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 104.105s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.63770445839223926251916320947640279538586923170469351519695422392395228826163
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 104.749s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.4587963242723091507935822618907842352824667559277500096958039752239266938226
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 69.243s, Critical Path: 0.00s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.31677244647652297698087856002558291428209630968919312636123496449798897353842
    Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.13237942858174813210672948269378164602220843357586639368064452665492679900840
    Line 379, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.50233690908567579847077303915623096043719809554501942522627952461674245688450
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.17045995218685433137604686834220943818463197164562110279311597793911729631083
    Line 382, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.17002749750474105543558575232586281232404995396970355008355977699743672286746
    Line 381, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.69475296145301632564445168273641467347173155916850068072210766763883946131824
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.113287219489769103592060732122089323421264809511335553217864974833713293871580
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.46288583771932146180919318478036434086970872695642504882814588032851483959801
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.67344261440793773030414462848224365099413486379123838641994177710336241662190
Line 423, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.493327 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.493327 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.72922066491880434330258798535447590268149274504105171589738193874349308712817
Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.606998 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.606998 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.45826998955258467973020044969346468925225965061420392229899141421593762191068
Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.399759 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.399759 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.88124579840423706824887493310202497028649651075851330405351901366842803555406
Line 406, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12018.442069 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.442069 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.87264064221419169568545064529464463517712506665913399498029325202293802832240
Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12018.522683 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.522683 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.58196862645964546984634726309599105706334689943954414517468141323592639673956
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12026.864677 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.864677 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.4705767793393637068850748503566626568106268736263651574628976698218711033578
Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 6626.998019 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (10283409591593219936842816247952521328953226809923109588018865014659020057683953914650578864126636235366118510465523769082135820279679110760677331448454236 [0xc4584250aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3420ef2a17f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 6626.998019 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.77549422679832550278995427836792859096456338419172260541882237895619076928603
Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 8703.816816 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (4088822498860305483628761888490362069724011908987763292466521540509834930263929016606266386253091566986168551267423514236525015189910013084983065619815516 [0x4e11bf80aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3c8470f717f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 8703.816816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.59790530575513665408098204657951791573623210229283979785803985641871456150209
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3640.077707 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'he98b55eb  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1a  a_opcode: 'h0  a_user: 'h26935  d_param: 'h0  d_source: 'h1a  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3640.077707 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.67940268822861004402133638726321979866352647309286208193777518528824983184717
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4370.052368 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'h5ed58d76  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h37  a_opcode: 'h0  a_user: 'h2690f  d_param: 'h0  d_source: 'h37  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4370.052368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.20130838383016474812981137174184498695219196402120667502287009133481632605038
    Line 1322, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.4522875038125809604865219346664650737754697278315250907196340207145078968348
    Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4228.055568 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4228.055568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.102863673073817425178009033966839894902521459491234204806513958690793923047747
    Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 5443.654776 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 5443.654776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 1 failures:
- Test chip_sw_lc_ctrl_rand_to_scrap has 1 failures.
  - 0.chip_sw_lc_ctrl_rand_to_scrap.71540368514569184040115736415999125508293733605427648580868057660225816357110
    Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log
```
  UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
  UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.108524565887568782616326668879517543826240598687951203329935262335573171216319
    Line 632, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 10452.362658 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 10452.362658 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.111843387257570829166209896363381602244778812708293869156713722548893889623674
    Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5386.257000 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5386.257000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.45349655266245902803235943735815580686068097545027328375378055251228248329527
    Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4548.295271 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4548.295271 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.104730010264544299715692296448620726493352170384807580407980557275961805358834
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 3979.434210 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 3979.434210 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.107655238661620577005744208456036678065732253709715680452843548500288405490114
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5298.983800 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5298.983800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.107451135519412167631231441172371404239571362797317958687152346194517553677309
    Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.49468180076148936053505494374166029919506071619377321966591765634063089631216
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3255.589595 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3255.589595 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.25680821304988769133784040585916908832127677952565504410422264808781518714848
    Line 376, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 15271.191334 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 15271.191334 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.41313936540182378827968011834240440774811085538289451105170440075559333522105
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.42036002614254135591886548710225723226832163667431641962703211835492843747394
    Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4757.073000 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4757.073000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```