DMA Simulation Results

Monday October 27 2025 16:03:52 UTC

GitHub Revision: cb622e0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	5.000s	334.356us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	5.000s	3.773ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	5.000s	738.446us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	71.213us	1	1	100.00
V1	csr_rw	dma_csr_rw	1.000s	27.320us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	5.000s	154.899us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	7.000s	1.064ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	1.000s	25.378us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	1.000s	27.320us	1	1	100.00
		dma_csr_aliasing	7.000s	1.064ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.433m	7.779ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	11.867m	69.395ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	2.783m	15.625ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	2.783m	15.625ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	11.867m	69.395ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	1.483m	13.094ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	2.783m	15.625ms	1	1	100.00
V2	dma_abort	dma_abort	9.000s	664.102us	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.200m	5.432ms	1	1	100.00
V2	alert_test	dma_alert_test	1.000s	23.877us	1	1	100.00
V2	intr_test	dma_intr_test	1.000s	21.938us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	2.000s	209.848us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	2.000s	209.848us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	71.213us	1	1	100.00
		dma_csr_rw	1.000s	27.320us	1	1	100.00
		dma_csr_aliasing	7.000s	1.064ms	1	1	100.00
		dma_same_csr_outstanding	2.000s	24.549us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	71.213us	1	1	100.00
		dma_csr_rw	1.000s	27.320us	1	1	100.00
		dma_csr_aliasing	7.000s	1.064ms	1	1	100.00
		dma_same_csr_outstanding	2.000s	24.549us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	20.000s	536.672us	1	1	100.00
		dma_generic_stress	1.483m	13.094ms	1	1	100.00
		dma_handshake_stress	2.783m	15.625ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	6.000s	1.301ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	4.000s	453.700us	1	1	100.00
		dma_sec_cm	2.000s	13.039us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	2.133m	110.526ms	1	1	100.00
		dma_longer_transfer	4.000s	135.205us	1	1	100.00
		dma_stress_all_with_rand_reset	10.000s	550.891us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.52475369742645098318604070974672202315101506562618628718300173416285410882672
      Line 99, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  550890602ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  550890602ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---