EDN Simulation Results

Monday October 27 2025 16:03:52 UTC

GitHub Revision: cb622e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.920s 43.514us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.080s 35.318us 1 1 100.00
V1 csr_rw edn_csr_rw 0.900s 17.129us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.530s 347.159us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.020s 62.122us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 0.940s 15.591us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.900s 17.129us 1 1 100.00
edn_csr_aliasing 1.020s 62.122us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 0.990s 57.680us 1 1 100.00
V2 csrng_commands edn_genbits 0.990s 57.680us 1 1 100.00
V2 genbits edn_genbits 0.990s 57.680us 1 1 100.00
V2 interrupts edn_intr 0.930s 38.927us 1 1 100.00
V2 alerts edn_alert 1.060s 37.470us 1 1 100.00
V2 errs edn_err 0.880s 29.748us 1 1 100.00
V2 disable edn_disable 0.840s 13.217us 1 1 100.00
edn_disable_auto_req_mode 0.820s 35.486us 1 1 100.00
V2 stress_all edn_stress_all 3.440s 414.981us 1 1 100.00
V2 intr_test edn_intr_test 0.850s 31.619us 1 1 100.00
V2 alert_test edn_alert_test 0.870s 87.907us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 1.190s 26.682us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 1.190s 26.682us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.080s 35.318us 1 1 100.00
edn_csr_rw 0.900s 17.129us 1 1 100.00
edn_csr_aliasing 1.020s 62.122us 1 1 100.00
edn_same_csr_outstanding 1.190s 60.075us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.080s 35.318us 1 1 100.00
edn_csr_rw 0.900s 17.129us 1 1 100.00
edn_csr_aliasing 1.020s 62.122us 1 1 100.00
edn_same_csr_outstanding 1.190s 60.075us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 3.190s 453.665us 1 1 100.00
edn_tl_intg_err 1.870s 264.319us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.870s 25.534us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.060s 37.470us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 3.190s 453.665us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 3.190s 453.665us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 3.190s 453.665us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 3.190s 453.665us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.060s 37.470us 1 1 100.00
edn_sec_cm 3.190s 453.665us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.060s 37.470us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 1.870s 264.319us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets