HMAC Simulation Results

Monday October 27 2025 16:03:52 UTC

GitHub Revision: cb622e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 3.130s 189.927us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.660s 13.837us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.730s 26.071us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.950s 2.189ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.540s 2.602ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.502m 17.429ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.730s 26.071us 1 1 100.00
hmac_csr_aliasing 5.540s 2.602ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 42.540s 14.403ms 1 1 100.00
V2 back_pressure hmac_back_pressure 19.660s 552.943us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.087m 5.442ms 1 1 100.00
hmac_test_sha384_vectors 6.827m 12.179ms 1 1 100.00
hmac_test_sha512_vectors 6.426m 11.936ms 1 1 100.00
hmac_test_hmac256_vectors 8.420s 315.243us 1 1 100.00
hmac_test_hmac384_vectors 8.630s 977.667us 1 1 100.00
hmac_test_hmac512_vectors 8.370s 255.273us 1 1 100.00
V2 burst_wr hmac_burst_wr 0.760s 110.719us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 5.580m 4.200ms 1 1 100.00
V2 error hmac_error 9.290s 7.403ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.604m 14.956ms 1 1 100.00
V2 save_and_restore hmac_smoke 3.130s 189.927us 1 1 100.00
hmac_long_msg 42.540s 14.403ms 1 1 100.00
hmac_back_pressure 19.660s 552.943us 1 1 100.00
hmac_datapath_stress 5.580m 4.200ms 1 1 100.00
hmac_burst_wr 0.760s 110.719us 1 1 100.00
hmac_stress_all 58.030s 3.007ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 3.130s 189.927us 1 1 100.00
hmac_long_msg 42.540s 14.403ms 1 1 100.00
hmac_back_pressure 19.660s 552.943us 1 1 100.00
hmac_datapath_stress 5.580m 4.200ms 1 1 100.00
hmac_wipe_secret 1.604m 14.956ms 1 1 100.00
hmac_test_sha256_vectors 3.087m 5.442ms 1 1 100.00
hmac_test_sha384_vectors 6.827m 12.179ms 1 1 100.00
hmac_test_sha512_vectors 6.426m 11.936ms 1 1 100.00
hmac_test_hmac256_vectors 8.420s 315.243us 1 1 100.00
hmac_test_hmac384_vectors 8.630s 977.667us 1 1 100.00
hmac_test_hmac512_vectors 8.370s 255.273us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 3.130s 189.927us 1 1 100.00
hmac_long_msg 42.540s 14.403ms 1 1 100.00
hmac_back_pressure 19.660s 552.943us 1 1 100.00
hmac_datapath_stress 5.580m 4.200ms 1 1 100.00
hmac_burst_wr 0.760s 110.719us 1 1 100.00
hmac_error 9.290s 7.403ms 1 1 100.00
hmac_wipe_secret 1.604m 14.956ms 1 1 100.00
hmac_test_sha256_vectors 3.087m 5.442ms 1 1 100.00
hmac_test_sha384_vectors 6.827m 12.179ms 1 1 100.00
hmac_test_sha512_vectors 6.426m 11.936ms 1 1 100.00
hmac_test_hmac256_vectors 8.420s 315.243us 1 1 100.00
hmac_test_hmac384_vectors 8.630s 977.667us 1 1 100.00
hmac_test_hmac512_vectors 8.370s 255.273us 1 1 100.00
hmac_stress_all 58.030s 3.007ms 1 1 100.00
V2 stress_all hmac_stress_all 58.030s 3.007ms 1 1 100.00
V2 alert_test hmac_alert_test 0.670s 13.993us 1 1 100.00
V2 intr_test hmac_intr_test 0.570s 13.982us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.470s 349.929us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.470s 349.929us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.660s 13.837us 1 1 100.00
hmac_csr_rw 0.730s 26.071us 1 1 100.00
hmac_csr_aliasing 5.540s 2.602ms 1 1 100.00
hmac_same_csr_outstanding 1.450s 148.259us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.660s 13.837us 1 1 100.00
hmac_csr_rw 0.730s 26.071us 1 1 100.00
hmac_csr_aliasing 5.540s 2.602ms 1 1 100.00
hmac_same_csr_outstanding 1.450s 148.259us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.850s 40.824us 1 1 100.00
hmac_tl_intg_err 1.380s 188.705us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.380s 188.705us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 3.130s 189.927us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.370s 455.846us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 4.270s 572.173us 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.570s 967.617us 1 1 100.00
TOTAL 28 28 100.00