I2C Simulation Results

Monday October 27 2025 16:03:52 UTC

GitHub Revision: `cb622e0`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	19.910s	28.916ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	28.890s	7.671ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.770s	30.802us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.770s	48.749us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.380s	117.749us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.520s	38.322us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.190s	21.371us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.770s	48.749us	1	1	100.00
		i2c_csr_aliasing	1.520s	38.322us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.160s	140.971us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	27.716m	36.176ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	2.359m	4.890ms	1	1	100.00
V2	host_override	i2c_host_override	0.960s	61.974us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.098m	9.289ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	53.350s	2.903ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.350s	121.823us	1	1	100.00
		i2c_host_fifo_fmt_empty	7.160s	342.793us	1	1	100.00
		i2c_host_fifo_reset_rx	2.680s	2.344ms	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.055m	68.918ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	18.780s	621.213us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.850s	28.133us	0	1	0.00
V2	target_glitch	i2c_target_glitch	3.360s	885.079us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	11.539m	52.235ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.180s	1.730ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	22.180s	10.205ms	1	1	100.00
		i2c_target_intr_smoke	6.660s	1.171ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.150s	167.883us	1	1	100.00
		i2c_target_fifo_reset_tx	1.020s	352.483us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	17.460s	7.054ms	1	1	100.00
		i2c_target_stress_rd	22.180s	10.205ms	1	1	100.00
		i2c_target_intr_stress_wr	7.560s	8.172ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.350s	16.845ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	6.250s	3.540ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.570s	3.371ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	19.390s	10.180ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.590s	764.023us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.150s	140.009us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	2.359m	4.890ms	1	1	100.00
		i2c_host_perf_precise	2.880s	237.053us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	18.780s	621.213us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.640s	94.095us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.220s	554.160us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.390s	433.440us	1	1	100.00
		i2c_target_nack_txstretch	1.250s	1.187ms	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.130s	988.146us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.080s	567.788us	1	1	100.00
V2	alert_test	i2c_alert_test	0.910s	25.400us	1	1	100.00
V2	intr_test	i2c_intr_test	0.780s	23.707us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.810s	43.353us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.810s	43.353us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.770s	30.802us	1	1	100.00
		i2c_csr_rw	0.770s	48.749us	1	1	100.00
		i2c_csr_aliasing	1.520s	38.322us	1	1	100.00
		i2c_same_csr_outstanding	0.920s	56.376us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.770s	30.802us	1	1	100.00
		i2c_csr_rw	0.770s	48.749us	1	1	100.00
		i2c_csr_aliasing	1.520s	38.322us	1	1	100.00
		i2c_same_csr_outstanding	0.920s	56.376us	1	1	100.00
V2		TOTAL			32	38	84.21
V2S	tl_intg_err	i2c_tl_intg_err	1.300s	55.025us	1	1	100.00
		i2c_sec_cm	0.990s	299.439us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.300s	55.025us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	10.920s	1.651ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.270s	67.974us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	27.460s	1.892ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			41	50	82.00

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 3 failures:

Test i2c_host_error_intr has 1 failures.

0.i2c_host_error_intr.8779784728274603274187407075040738985248055091301879241448991580397947248363
Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 140971362 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 140971362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.54494505578536543023855188978487869434146372122196587302158909288839711670293
Line 134, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 36175519159 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 36175519159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.10782788446656212823886558825524961660315657127776182396030304055415310479356
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  28132770 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  28132770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.98957041117343707761277008487233282092288145796817587327375127082796075649566
    Line 87, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1651111871 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1651111871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.81689093307370929529093995362729279311946664823642297688475523510524702165061
    Line 112, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1891680053 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1891680053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test i2c_target_glitch has 1 failures.
  - 0.i2c_target_glitch.93624588723208457342975911454149244487170543032667124388486226708059266115942
    Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
```
  UVM_ERROR @ 885079089 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 885079089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.22119383494369585958406369859927497177838425534319767579475956540889559854624
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  67974271 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 146 [0x92])
  UVM_INFO @  67974271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.80704432227552197515434204803194022983344119409586461511979528026818211501028
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10180369155 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10180369155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:
- Test i2c_target_nack_txstretch has 1 failures.
  - 0.i2c_target_nack_txstretch.29805801872178766299133875546980348091451847215618355911875088569598746478692
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 1186509582 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 1186509582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```