KEYMGR Simulation Results

Monday October 27 2025 16:03:52 UTC

GitHub Revision: cb622e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 1.480s 100.379us 1 1 100.00
V1 random keymgr_random 6.490s 400.528us 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.000s 29.405us 1 1 100.00
V1 csr_rw keymgr_csr_rw 1.010s 201.873us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 10.690s 650.740us 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 2.680s 111.819us 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.360s 58.047us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.010s 201.873us 1 1 100.00
keymgr_csr_aliasing 2.680s 111.819us 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 2.640s 78.069us 1 1 100.00
V2 sideload keymgr_sideload 2.790s 335.009us 1 1 100.00
keymgr_sideload_kmac 1.970s 86.996us 1 1 100.00
keymgr_sideload_aes 36.450s 7.114ms 1 1 100.00
keymgr_sideload_otbn 1.900s 49.435us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 3.640s 176.006us 1 1 100.00
V2 lc_disable keymgr_lc_disable 2.120s 241.155us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 2.560s 112.389us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 3.030s 91.228us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 1.660s 42.123us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 1.840s 50.737us 1 1 100.00
V2 stress_all keymgr_stress_all 16.120s 474.089us 1 1 100.00
V2 intr_test keymgr_intr_test 0.620s 34.100us 1 1 100.00
V2 alert_test keymgr_alert_test 0.700s 16.131us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 2.020s 188.148us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 2.020s 188.148us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.000s 29.405us 1 1 100.00
keymgr_csr_rw 1.010s 201.873us 1 1 100.00
keymgr_csr_aliasing 2.680s 111.819us 1 1 100.00
keymgr_same_csr_outstanding 1.860s 53.845us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.000s 29.405us 1 1 100.00
keymgr_csr_rw 1.010s 201.873us 1 1 100.00
keymgr_csr_aliasing 2.680s 111.819us 1 1 100.00
keymgr_same_csr_outstanding 1.860s 53.845us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 7.520s 2.750ms 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 7.520s 2.750ms 1 1 100.00
keymgr_tl_intg_err 3.060s 229.116us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 2.570s 662.230us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 2.570s 662.230us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 2.570s 662.230us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 2.570s 662.230us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 5.600s 189.327us 1 1 100.00
V2S prim_count_check keymgr_sec_cm 7.520s 2.750ms 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 7.520s 2.750ms 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 3.060s 229.116us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 2.570s 662.230us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 2.640s 78.069us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 6.490s 400.528us 1 1 100.00
keymgr_csr_rw 1.010s 201.873us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 6.490s 400.528us 1 1 100.00
keymgr_csr_rw 1.010s 201.873us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 6.490s 400.528us 1 1 100.00
keymgr_csr_rw 1.010s 201.873us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 2.120s 241.155us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 1.660s 42.123us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 1.660s 42.123us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 6.490s 400.528us 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 1.830s 68.586us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 7.520s 2.750ms 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 7.520s 2.750ms 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 7.520s 2.750ms 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 1.540s 30.171us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 2.120s 241.155us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 7.520s 2.750ms 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 7.520s 2.750ms 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 7.520s 2.750ms 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 1.540s 30.171us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 1.540s 30.171us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 7.520s 2.750ms 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 1.540s 30.171us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 7.520s 2.750ms 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 1.540s 30.171us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 14.910s 1.421ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00