| V1 |
smoke |
keymgr_dpe_smoke |
19.640s |
4.483ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
1.140s |
36.958us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
1.000s |
14.937us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
6.800s |
2.279ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
4.080s |
312.539us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.300s |
49.293us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
1.000s |
14.937us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.080s |
312.539us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
0.720s |
110.559us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
1.050s |
264.021us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
0.990s |
19.325us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
0.990s |
19.325us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
1.140s |
36.958us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.000s |
14.937us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.080s |
312.539us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.760s |
144.568us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
1.140s |
36.958us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.000s |
14.937us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.080s |
312.539us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.760s |
144.568us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
10.130s |
1.797ms |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
3.200s |
368.368us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
2.010s |
125.535us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
2.010s |
125.535us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
2.010s |
125.535us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
2.010s |
125.535us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
5.640s |
218.146us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
10.130s |
1.797ms |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
10.130s |
1.797ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |