| V1 |
smoke |
kmac_smoke |
7.290s |
2.687ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
0.960s |
69.287us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
1.100s |
36.047us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
11.430s |
5.574ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
3.790s |
834.974us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
1.900s |
290.538us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
1.100s |
36.047us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.790s |
834.974us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.980s |
30.013us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.350s |
39.783us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
21.125m |
15.379ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
17.433m |
67.091ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
33.874m |
840.266ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
31.062m |
385.875ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
25.474m |
69.444ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
16.273m |
32.161ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
2.460m |
27.818ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
28.579m |
113.340ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.920s |
77.127us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
3.520s |
417.820us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
4.210m |
4.004ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
3.474m |
26.039ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
4.428m |
31.769ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
1.002m |
2.989ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
3.142m |
23.103ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
2.040s |
168.803us |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
7.430s |
92.856us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
0.940s |
83.762us |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
4.540s |
90.035us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
47.330s |
13.257ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
22.340s |
1.602ms |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
12.675m |
31.489ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
1.070s |
19.546us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
1.200s |
35.680us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
1.870s |
40.260us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
1.870s |
40.260us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
0.960s |
69.287us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.100s |
36.047us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.790s |
834.974us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.180s |
637.608us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
0.960s |
69.287us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.100s |
36.047us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.790s |
834.974us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.180s |
637.608us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
2.360s |
188.156us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
2.360s |
188.156us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
2.360s |
188.156us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
2.360s |
188.156us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
2.160s |
65.899us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
25.670s |
14.356ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
3.370s |
150.902us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
3.370s |
150.902us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
22.340s |
1.602ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
7.290s |
2.687ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
4.210m |
4.004ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
2.360s |
188.156us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
25.670s |
14.356ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
25.670s |
14.356ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
25.670s |
14.356ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
7.290s |
2.687ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
22.340s |
1.602ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
25.670s |
14.356ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
11.460s |
200.117us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
7.290s |
2.687ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
2.601m |
55.513ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |