cb622e0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 4.440s | 2.217ms | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 1.410s | 315.258us | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 1.420s | 379.078us | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 3.830s | 6.122ms | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 1.560s | 967.894us | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 8.210s | 8.316ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 7.240s | 3.173ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 12.970s | 6.076ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 16.510s | 13.925ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 0.770s | 270.197us | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 1.100s | 173.467us | 1 | 1 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 1.010s | 202.509us | 1 | 1 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 0.720s | 88.882us | 0 | 1 | 0.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 0.650s | 260.837us | 1 | 1 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 2.490s | 1.882ms | 1 | 1 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.900s | 99.610us | 1 | 1 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 2.380s | 965.520us | 1 | 1 | 100.00 |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 0.770s | 270.197us | 1 | 1 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 1.340s | 642.787us | 1 | 1 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 1.110s | 599.716us | 1 | 1 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 1.010s | 202.509us | 1 | 1 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.740s | 149.494us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 1.330s | 531.468us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 1.540s | 107.047us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 54.950s | 60.763ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 21.740s | 10.688ms | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 0.740s | 96.018us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 21.740s | 10.688ms | 1 | 1 | 100.00 |
| rv_dm_csr_rw | 1.540s | 107.047us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.870s | 114.237us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.990s | 82.911us | 1 | 1 | 100.00 |
| V1 | TOTAL | 25 | 27 | 92.59 | |||
| V2 | idcode | rv_dm_smoke | 4.440s | 2.217ms | 1 | 1 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.110s | 564.371us | 1 | 1 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0.830s | 276.569us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 0.840s | 169.325us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 1.130s | 370.411us | 1 | 1 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 4.654m | 300.000ms | 0 | 1 | 0.00 |
| rv_dm_delayed_resp_sba_tl_access | 4.408m | 300.000ms | 0 | 1 | 0.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 2.265m | 300.000ms | 0 | 1 | 0.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 8.086m | 300.000ms | 0 | 1 | 0.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 1.680s | 337.699us | 0 | 1 | 0.00 |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 2.380s | 3.647ms | 1 | 1 | 100.00 |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 1.060s | 177.116us | 1 | 1 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 0.780s | 114.497us | 0 | 1 | 0.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 21.370s | 12.963ms | 0 | 1 | 0.00 |
| rv_dm_tap_fsm_rand_reset | 1.190s | 141.083us | 0 | 1 | 0.00 | ||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 1.430s | 322.704us | 1 | 1 | 100.00 |
| V2 | stress_all | rv_dm_stress_all | 4.090s | 1.658ms | 0 | 1 | 0.00 |
| V2 | alert_test | rv_dm_alert_test | 0.670s | 45.114us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 2.270s | 164.806us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 2.270s | 164.806us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 21.740s | 10.688ms | 1 | 1 | 100.00 |
| rv_dm_csr_hw_reset | 1.330s | 531.468us | 1 | 1 | 100.00 | ||
| rv_dm_csr_rw | 1.540s | 107.047us | 1 | 1 | 100.00 | ||
| rv_dm_same_csr_outstanding | 2.860s | 449.489us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 21.740s | 10.688ms | 1 | 1 | 100.00 |
| rv_dm_csr_hw_reset | 1.330s | 531.468us | 1 | 1 | 100.00 | ||
| rv_dm_csr_rw | 1.540s | 107.047us | 1 | 1 | 100.00 | ||
| rv_dm_same_csr_outstanding | 2.860s | 449.489us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 10 | 19 | 52.63 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 2.110s | 838.599us | 1 | 1 | 100.00 |
| rv_dm_tl_intg_err | 11.450s | 1.252ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 11.450s | 1.252ms | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 2.380s | 3.647ms | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 1.100s | 63.228us | 0 | 1 | 0.00 | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 2.380s | 3.647ms | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 1.100s | 63.228us | 0 | 1 | 0.00 | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 4.440s | 2.217ms | 1 | 1 | 100.00 |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 1.030s | 205.537us | 0 | 1 | 0.00 |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 0.750s | 119.093us | 1 | 1 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 0.750s | 119.093us | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 1.030s | 205.537us | 0 | 1 | 0.00 |
| V2S | TOTAL | 3 | 5 | 60.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 0.780s | 132.038us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | rv_dm_scanmode | 3.675m | 300.000ms | 0 | 1 | 0.00 | |
| TOTAL | 38 | 53 | 71.70 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
Test rv_dm_sba_tl_access has 1 failures.
0.rv_dm_sba_tl_access.17678581124435186522256295159542714409527263405327869202950871079987903451623
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
0.rv_dm_delayed_resp_sba_tl_access.31822845468190978120680397944157758317091867698740531493901680405957242342173
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_bad_sba_tl_access has 1 failures.
0.rv_dm_bad_sba_tl_access.19320157971886302354873909672829408593225398684857261269198534349059976575882
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 1 failures.
0.rv_dm_autoincr_sba_tl_access.8420308136655245432139351799051655019432787015015089381443415240214426799790
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_scanmode has 1 failures.
0.rv_dm_scanmode.23872837394212585604491245039215086517287855884546636429486815008934695122018
Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_scanmode/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs * [])` has 2 failures:
Test rv_dm_hart_unavail has 1 failures.
0.rv_dm_hart_unavail.110682385732997087500133172345638505138556617233464230321264785449301193074643
Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest/run.log
UVM_ERROR @ 114497329 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 114497329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 1 failures.
0.rv_dm_stress_all.61386743871682851420107493285171834817355036818387062451888015638217638899661
Line 79, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1657502744 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1657502744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access has 1 failures:
0.rv_dm_tap_fsm.66380681895958659317311739764455053680815900233451730162650465210060276318943
Line 110, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
Error-[NOA] Null object access
src/lowrisc_dv_cip_lib_0/seq_lib/cip_base_vseq.sv, 638
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@7256) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tap_fsm_rand_reset.44630646265721229609586341478750043733793859081183009636905932302850784109290
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 141082584 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@7256) { a_addr: 'hc4d5f790 a_data: 'h2d2a7b76 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h24 a_opcode: 'h4 a_user: 'h191a5 d_param: 'h0 d_source: 'h24 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 141082584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs * [])` has 1 failures:
0.rv_dm_mem_tl_access_resuming.70535347027307341661162773257319673420536020873550661842705239815170080375528
Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest/run.log
UVM_ERROR @ 88882161 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 88882161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 1 failures:
0.rv_dm_jtag_dmi_debug_disabled.24655306036168015272423546263071421577993087958295750807297806118227519854734
Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 337698509 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2301686594 [0x8930f342] vs 0 [0x0])
UVM_INFO @ 337698509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_debug_disabled_vseq.sv:33) [rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output) has 1 failures:
0.rv_dm_debug_disabled.1820023913389574926727695980651749144881074684424269848147862256159823212284
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_debug_disabled/latest/run.log
UVM_ERROR @ 63228127 ps: (rv_dm_debug_disabled_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)
UVM_INFO @ 63228127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [*] vs * [*]) has 1 failures:
0.rv_dm_buffered_enable.57680350952186580956605483356846414241748082832605417090430993876894375618948
Line 80, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_buffered_enable/latest/run.log
UVM_ERROR @ 205537407 ps: (rv_dm_buffered_enable_vseq.sv:164) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (0 [0x0] vs 1 [0x1])
UVM_INFO @ 205537407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6342) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_stress_all_with_rand_reset.39046474784165078034277894670633075589663553408773483597531022594834790733457
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 132037889 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6342) { a_addr: 'h601694a4 a_data: 'hd5ec2c33 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2e a_opcode: 'h4 a_user: 'h1a553 d_param: 'h0 d_source: 'h2e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 132037889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5600) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_csr_mem_rw_with_rand_reset.81315822763143955538194359397540143171218899833514925538032688467618098880459
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 96017622 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5600) { a_addr: 'hc93a95a8 a_data: 'h58e2ee22 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hc9 a_opcode: 'h4 a_user: 'h19030 d_param: 'h0 d_source: 'hc9 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 96017622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---