RV_TIMER Simulation Results

Monday October 27 2025 16:03:52 UTC

GitHub Revision: cb622e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.400s	70.287us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.780s	15.800us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.870s	12.689us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.770s	1.379ms	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.880s	526.440us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.820s	30.578us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.870s	12.689us	1	1	100.00
		rv_timer_csr_aliasing	0.880s	526.440us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.860s	113.510us	0	1	0.00
V2	disabled	rv_timer_disabled	1.060s	509.428us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	3.988m	672.347ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	3.988m	672.347ms	1	1	100.00
V2	stress	rv_timer_stress_all	3.630s	1.738ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.690s	30.407us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.780s	33.829us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.220s	458.161us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.220s	458.161us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.780s	15.800us	1	1	100.00
		rv_timer_csr_rw	0.870s	12.689us	1	1	100.00
		rv_timer_csr_aliasing	0.880s	526.440us	1	1	100.00
		rv_timer_same_csr_outstanding	0.920s	35.880us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.780s	15.800us	1	1	100.00
		rv_timer_csr_rw	0.870s	12.689us	1	1	100.00
		rv_timer_csr_aliasing	0.880s	526.440us	1	1	100.00
		rv_timer_same_csr_outstanding	0.920s	35.880us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	1.110s	102.073us	1	1	100.00
		rv_timer_tl_intg_err	1.290s	2.535ms	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.290s	2.535ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.790s	58.565us	0	1	0.00
V3	max_value	rv_timer_max	1.120s	168.756us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	5.530s	3.273ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			15	19	78.95

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.42120490475792440036709249617190107784792260089280363078845364599912268070359
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @  58565494 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x6670a904) == 0x1
        UVM_INFO @  58565494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.113064187168548937175680055881179429112468954420614021201397542419119913447683
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 113510444 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x29f27f04) == 0x1
        UVM_INFO @ 113510444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:365) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.42402410710112304806277787720513155825847215858201374827565536277849138091123
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 168755629 ps: (rv_timer_scoreboard.sv:365) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
        UVM_INFO @ 168755629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 1 failures:

  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 0.rv_timer_stress_all_with_rand_reset.19240077774898709044891645063273056570208479515267760765226155233334791340610
      Line 113, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 3272971174 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
        UVM_INFO @ 3272971174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---