SPI_DEVICE/1R1W Simulation Results

Monday October 27 2025 16:03:52 UTC

GitHub Revision: cb622e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	4.329m	39.413ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.010s	17.689us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.070s	649.488us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	22.200s	2.008ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.620s	3.250ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.970s	26.619us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.070s	649.488us	1	1	100.00
		spi_device_csr_aliasing	11.620s	3.250ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.630s	156.182us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.700s	52.960us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.110s	51.005us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.830s	950.479ns	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.860s	6.862us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	3.230s	163.616us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	3.230s	163.616us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	1.090s	43.263us	1	1	100.00
		spi_device_tpm_sts_read	0.920s	25.148us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	13.250s	7.134ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.580s	1.631ms	1	1	100.00
		spi_device_flash_all	0.840s	15.472us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.630s	676.903us	1	1	100.00
		spi_device_flash_all	0.840s	15.472us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.630s	676.903us	1	1	100.00
		spi_device_flash_all	0.840s	15.472us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	0.840s	15.472us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	11.440s	2.504ms	1	1	100.00
		spi_device_flash_all	0.840s	15.472us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	11.440s	2.504ms	1	1	100.00
		spi_device_flash_all	0.840s	15.472us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	11.440s	2.504ms	1	1	100.00
		spi_device_flash_all	0.840s	15.472us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	11.440s	2.504ms	1	1	100.00
		spi_device_flash_all	0.840s	15.472us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	11.440s	2.504ms	1	1	100.00
		spi_device_flash_all	0.840s	15.472us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.030s	62.031us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.350s	887.178us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.350s	887.178us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.350s	887.178us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.070s	173.767us	1	1	100.00
		spi_device_read_buffer_direct	7.310s	5.317ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.350s	887.178us	1	1	100.00
		spi_device_flash_all	0.840s	15.472us	1	1	100.00
V2	quad_spi	spi_device_flash_all	0.840s	15.472us	1	1	100.00
V2	dual_spi	spi_device_flash_all	0.840s	15.472us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.640s	114.326us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.640s	114.326us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	4.329m	39.413ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	4.900m	43.862ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.695m	32.815ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.700s	14.177us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.850s	48.598us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.480s	121.693us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.480s	121.693us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.010s	17.689us	1	1	100.00
		spi_device_csr_rw	2.070s	649.488us	1	1	100.00
		spi_device_csr_aliasing	11.620s	3.250ms	1	1	100.00
		spi_device_same_csr_outstanding	3.750s	119.857us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.010s	17.689us	1	1	100.00
		spi_device_csr_rw	2.070s	649.488us	1	1	100.00
		spi_device_csr_aliasing	11.620s	3.250ms	1	1	100.00
		spi_device_same_csr_outstanding	3.750s	119.857us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.050s	384.922us	1	1	100.00
		spi_device_tl_intg_err	10.910s	2.749ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.910s	2.749ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	42.070s	8.257ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.61492569641116733732012291606967630642847697800002020520639422556928195180043
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    770479 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[80])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    770479 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    770479 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[976])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.83024851584028813090147321831321443018674241802415371981024826930492754609171
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4463401 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1e317a [111100011000101111010] vs 0x0 [0])
        UVM_ERROR @   4477401 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x95688c [100101010110100010001100] vs 0x0 [0])
        UVM_ERROR @   4519401 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x82fd [1000001011111101] vs 0x0 [0])
        UVM_ERROR @   4576401 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5bf7bd [10110111111011110111101] vs 0x0 [0])
        UVM_ERROR @   4666401 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfa7f4a [111110100111111101001010] vs 0x0 [0])