SPI_HOST Simulation Results

Monday October 27 2025 16:03:52 UTC

GitHub Revision: cb622e0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	30.000s	6.232ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	49.439us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	16.704us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	131.499us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	51.393us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	55.805us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	16.704us	1	1	100.00
		spi_host_csr_aliasing	1.000s	51.393us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	86.372us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	22.623us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	1.000s	34.140us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.000s	160.449us	1	1	100.00
		spi_host_error_cmd	1.000s	16.281us	1	1	100.00
		spi_host_event	7.000s	1.218ms	1	1	100.00
V2	clock_rate	spi_host_speed	2.000s	26.635us	1	1	100.00
V2	speed	spi_host_speed	2.000s	26.635us	1	1	100.00
V2	chip_select_timing	spi_host_speed	2.000s	26.635us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	2.000s	59.398us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.000s	75.154us	1	1	100.00
V2	cpol_cpha	spi_host_speed	2.000s	26.635us	1	1	100.00
V2	full_cycle	spi_host_speed	2.000s	26.635us	1	1	100.00
V2	duplex	spi_host_smoke	30.000s	6.232ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	30.000s	6.232ms	1	1	100.00
V2	stress_all	spi_host_stress_all	21.000s	3.570ms	1	1	100.00
V2	spien	spi_host_spien	2.000s	250.852us	1	1	100.00
V2	stall	spi_host_status_stall	5.117m	54.419ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	321.413us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	2.000s	160.449us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	137.392us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	30.025us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	46.742us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	46.742us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	49.439us	1	1	100.00
		spi_host_csr_rw	2.000s	16.704us	1	1	100.00
		spi_host_csr_aliasing	1.000s	51.393us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	23.492us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	49.439us	1	1	100.00
		spi_host_csr_rw	2.000s	16.704us	1	1	100.00
		spi_host_csr_aliasing	1.000s	51.393us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	23.492us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	109.351us	1	1	100.00
		spi_host_sec_cm	2.000s	168.989us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	109.351us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	5.350m	29.544ms	1	1	100.00
		TOTAL			26	26	100.00