SRAM_CTRL/MAIN Simulation Results

Monday October 27 2025 16:03:52 UTC

GitHub Revision: cb622e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.190m	3.369ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.990s	11.678us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.770s	13.661us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.860s	672.181us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.730s	43.632us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.950s	352.494us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.770s	13.661us	1	1	100.00
		sram_ctrl_csr_aliasing	0.730s	43.632us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.923m	6.999ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.848m	6.745ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	4.525m	2.392ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.440m	55.697ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	29.331m	805.849ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1.725m	3.086ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	17.420s	4.393ms	1	1	100.00
V2	executable	sram_ctrl_executable	8.075m	17.911ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	4.750s	513.070us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.422m	21.696ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	50.270s	7.581ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	53.340s	3.875ms	1	1	100.00
		sram_ctrl_throughput_w_readback	23.110s	819.215us	1	1	100.00
V2	regwen	sram_ctrl_regwen	24.330s	6.625ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.520s	683.903us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	37.619m	296.769ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.950s	16.043us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.260s	145.039us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.260s	145.039us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.990s	11.678us	1	1	100.00
		sram_ctrl_csr_rw	0.770s	13.661us	1	1	100.00
		sram_ctrl_csr_aliasing	0.730s	43.632us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.840s	51.527us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.990s	11.678us	1	1	100.00
		sram_ctrl_csr_rw	0.770s	13.661us	1	1	100.00
		sram_ctrl_csr_aliasing	0.730s	43.632us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.840s	51.527us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	34.450s	7.135ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.880s	32.286us	0	1	0.00
		sram_ctrl_tl_intg_err	1.500s	157.871us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.880s	32.286us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.500s	157.871us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	24.330s	6.625ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	24.330s	6.625ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.770s	13.661us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.075m	17.911ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.075m	17.911ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.075m	17.911ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	17.420s	4.393ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	7.070s	3.037ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	34.450s	7.135ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	7.120s	2.643ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.190m	3.369ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.190m	3.369ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.075m	17.911ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.880s	32.286us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	17.420s	4.393ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.880s	32.286us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.880s	32.286us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.190m	3.369ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.880s	32.286us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.890s	2.959ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.101494455562014953171980222731111511864015938947925715569868507204908677774041
      Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 26660764ps failed at 26660764ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        UVM_ERROR @  32285742 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  32285742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]