UART Simulation Results

Monday October 27 2025 16:03:52 UTC

GitHub Revision: cb622e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	0.960s	98.080us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.920s	1.070ms	1	1	100.00
V1	csr_rw	uart_csr_rw	0.750s	11.945us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.150s	89.488us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.750s	362.021us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.650s	17.450us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.750s	11.945us	1	1	100.00
		uart_csr_aliasing	0.750s	362.021us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	53.120s	93.007ms	1	1	100.00
V2	parity	uart_smoke	0.960s	98.080us	1	1	100.00
		uart_tx_rx	53.120s	93.007ms	1	1	100.00
V2	parity_error	uart_intr	25.220s	21.378ms	1	1	100.00
		uart_rx_parity_err	15.040s	18.368ms	1	1	100.00
V2	watermark	uart_tx_rx	53.120s	93.007ms	1	1	100.00
		uart_intr	25.220s	21.378ms	1	1	100.00
V2	fifo_full	uart_fifo_full	2.235m	94.410ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	6.560s	25.051ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	13.300s	12.323ms	1	1	100.00
V2	rx_frame_err	uart_intr	25.220s	21.378ms	1	1	100.00
V2	rx_break_err	uart_intr	25.220s	21.378ms	1	1	100.00
V2	rx_timeout	uart_intr	25.220s	21.378ms	1	1	100.00
V2	perf	uart_perf	6.156m	14.242ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.660s	1.512ms	1	1	100.00
V2	line_loopback	uart_loopback	2.660s	1.512ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	3.790s	11.809ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	11.520s	36.494ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	5.340s	1.412ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	9.670s	2.517ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	8.251m	67.115ms	1	1	100.00
V2	stress_all	uart_stress_all	32.800s	63.565ms	0	1	0.00
V2	alert_test	uart_alert_test	0.830s	12.556us	1	1	100.00
V2	intr_test	uart_intr_test	0.760s	100.306us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	0.960s	315.101us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	0.960s	315.101us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.920s	1.070ms	1	1	100.00
		uart_csr_rw	0.750s	11.945us	1	1	100.00
		uart_csr_aliasing	0.750s	362.021us	1	1	100.00
		uart_same_csr_outstanding	0.750s	21.598us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.920s	1.070ms	1	1	100.00
		uart_csr_rw	0.750s	11.945us	1	1	100.00
		uart_csr_aliasing	0.750s	362.021us	1	1	100.00
		uart_same_csr_outstanding	0.750s	21.598us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	1.310s	65.311us	1	1	100.00
		uart_tl_intg_err	1.060s	196.085us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.060s	196.085us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	50.990s	15.049ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.43271190593355433061064603738543705563018282666653908006362443441141781907997
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 11804990244 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 11804990244 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 11805230244 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 11805230244 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 11805390244 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
      

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.76236865833211135907445561793285444180505430733718837231625583784085558481285
      Line 124, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 63051863967 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6,                                 clk_pulses: 0
        UVM_ERROR @ 63051889608 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 63051940890 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (244 [0xf4] vs 215 [0xd7]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 63051966531 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 63051992172 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (244 [0xf4] vs 255 [0xff]) reg name: uart_reg_block.rdata