CHIP Simulation Results

Monday October 27 2025 16:03:52 UTC

GitHub Revision: `cb622e0`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.996m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.996m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	50.848s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	21.248s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	11.931s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.635m	4.485ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.635m	4.485ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.635m	4.485ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	33.490s	10.320us	0	1	0.00
		chip_sw_example_manufacturer	2.224m		0	1	0.00
		chip_sw_example_concurrency	5.889m	5.586ms	1	1	100.00
		chip_sw_uart_smoketest_signed	15.955s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.620s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	8.480s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	8.480s		0	1	0.00
V1	xbar_smoke	xbar_smoke	19.950s	61.270us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.842m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	9.541m	8.007ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.302m	4.919ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	15.392s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	13.605s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	13.665s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	14.488s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.070s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.070s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.937m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.978m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.234m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.234m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.393m	3.070ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.493m	4.052ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.974m	9.652ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	14.555s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	13.408s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	2.544m	3.086ms	0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.879m	4.557ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	20.578m	18.027ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	20.578m	18.027ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	17.864s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.261m	5.015ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.261m	5.015ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.535m	18.027ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.262m	5.652ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.896m	4.386ms	1	1	100.00
		chip_sw_aes_idle	5.017m	5.966ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.365m	4.632ms	1	1	100.00
		chip_sw_kmac_idle	4.190m	3.961ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	14.122m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	13.422m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	13.590m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.512m	12.027ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	14.012s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.972s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.195s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.432s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.387s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.382s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.024s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	14.012s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.972s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.195s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.432s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.387s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.382s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.024s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.563s		0	1	0.00
		chip_sw_aes_enc_jitter_en	36.510s	10.400us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	37.410s	10.160us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	38.980s	10.320us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	38.650s	10.120us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.649s		0	1	0.00
		chip_sw_clkmgr_jitter	3.528m	4.575ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.427m	3.561ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	12.806s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	38.980s	10.360us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	40.600s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	37.480s	10.360us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	43.860s	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	37.160s	10.340us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.623s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.860s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.541s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.845s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	20.063m	14.786ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.744m	17.929ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.261m	5.015ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	12.056s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.744m	17.929ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	13.792s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	15.713s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	14.415s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	16.777s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	15.228s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	20.063m	14.786ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.974m	9.652ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	22.957m	20.027ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.342m	8.290ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	9.031m	10.463ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.902m	5.020ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	20.063m	14.786ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	15.876s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	16.051s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	20.063m	14.786ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.122s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	9.031m	10.463ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	12.154s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.450s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.946s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.428s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.301s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	11.975s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	16.051s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	12.416s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	16.038s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.416s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.416s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.416s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.551m	8.521ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	17.319s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	19.263s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	20.563s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	13.237s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.416s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.174m	5.354ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	11.059m	14.640ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	13.701s		0	1	0.00
		chip_prim_tl_access	11.881m	15.764ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	14.012s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.972s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.195s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.432s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.387s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.382s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.024s		0	1	0.00
		chip_rv_dm_lc_disabled	2.544m	3.086ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.750m	4.584ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	36.510s	10.400us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.394m	3.622ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.017m	5.966ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.818m	4.067ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	37.410s	10.160us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.365m	4.632ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.076m	4.765ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.802m	4.414ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	38.650s	10.120us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.174m	5.354ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.416s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	31.500s	10.400us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.755m	3.984ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.190m	3.961ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.572s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.572s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.622s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.165m	4.873ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.916s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.174m	5.354ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	38.980s	10.320us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	13.988s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	12.563s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.896m	4.386ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.896m	4.386ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.896m	4.386ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	9.347m	5.676ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	11.059m	14.640ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	11.059m	14.640ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.261m	6.759ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.649s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.701s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	20.063m	14.786ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.234m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.416s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	9.347m	5.676ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.174m	5.354ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.261m	6.759ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.587m	3.877ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	9.347m	5.676ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.174m	5.354ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.261m	6.759ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.587m	3.877ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.416s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.966s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	16.038s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	17.319s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	19.263s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	20.563s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	13.237s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.416s		0	1	0.00
		chip_prim_tl_access	11.881m	15.764ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	11.881m	15.764ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	12.030s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.497s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.860s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.563s		0	1	0.00
		chip_sw_aes_enc_jitter_en	36.510s	10.400us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	37.410s	10.160us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	38.980s	10.320us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	38.650s	10.120us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.649s		0	1	0.00
		chip_sw_clkmgr_jitter	3.528m	4.575ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	4.737m	5.307ms	0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	4.737m	5.307ms	0	1	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	3.872m	3.528ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.350m	4.774ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.718m	5.326ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.144m	5.379ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.298m	4.250ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	5.731m	5.951ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.587m	3.877ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	22.957m	20.027ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	22.957m	20.027ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.466m	3.440ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.452m	3.527ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.364m	3.845ms	1	1	100.00
		chip_sw_csrng_smoketest	3.568m	5.566ms	1	1	100.00
		chip_sw_gpio_smoketest	4.481m	5.226ms	1	1	100.00
		chip_sw_hmac_smoketest	4.660m	6.252ms	1	1	100.00
		chip_sw_kmac_smoketest	4.148m	5.028ms	1	1	100.00
		chip_sw_otbn_smoketest	4.519m	5.353ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.577m	5.095ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.627m	4.162ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.768m	5.576ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.728m	4.114ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.196m	4.147ms	1	1	100.00
		chip_sw_uart_smoketest	3.334m	3.690ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.510s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	15.955s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.842m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	13.835s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.334m	4.102ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	43.307m	60.000ms	0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.170m	4.983ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.921m	4.592ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	13.927s		0	1	0.00
		chip_rv_dm_lc_disabled	2.544m	3.086ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	14.701s		0	1	0.00
		chip_sw_lc_walkthrough_prod	14.677s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	13.916s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.839s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	13.927s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	7.883m	7.057ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	6.818m	7.940ms	1	1	100.00
		rom_volatile_raw_unlock	11.743s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.437s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.571m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.941m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.727m	5.100ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.727m	5.100ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	8.480s		0	1	0.00
		chip_same_csr_outstanding	10.890s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	8.480s		0	1	0.00
		chip_same_csr_outstanding	10.890s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.138m	61.674us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.610s	11.993us	1	1	100.00
		xbar_smoke_large_delays	4.718m	2.400ms	1	1	100.00
		xbar_smoke_slow_rsp	6.887m	2.507ms	1	1	100.00
		xbar_random_zero_delays	50.510s	43.194us	1	1	100.00
		xbar_random_large_delays	2.865m	1.469ms	1	1	100.00
		xbar_random_slow_rsp	27.892m	10.311ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	22.890s	39.831us	1	1	100.00
		xbar_error_and_unmapped_addr	43.990s	91.788us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	12.640s	9.010us	1	1	100.00
		xbar_error_and_unmapped_addr	43.990s	91.788us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	12.830s	18.730us	1	1	100.00
		xbar_access_same_device_slow_rsp	32.837m	12.452ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.099m	174.230us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	10.008m	1.537ms	1	1	100.00
		xbar_stress_all_with_error	3.188m	543.851us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	14.740m	507.235us	1	1	100.00
		xbar_stress_all_with_reset_error	3.659m	229.325us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.378s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.023s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.236s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.777s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.233s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.280s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.541s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.539s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	12.397s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.642s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.573s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.800s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.646s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	40.461s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	42.896s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	41.428s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	38.393s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	41.987s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	42.229s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	38.519s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	41.306s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	29.239s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	38.655s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	38.437s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	34.549s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	36.986s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	34.117s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	36.115s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.567s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.176s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	14.471s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.596s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.981s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	16.097s		0	1	0.00
		rom_e2e_asm_init_dev	12.076s		0	1	0.00
		rom_e2e_asm_init_prod	12.767s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.772s		0	1	0.00
		rom_e2e_asm_init_rma	11.923s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	12.502s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.714s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.680s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	12.681s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.133m	4.362ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.125m	3.723ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.736s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.914s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.505s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.415s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	20.063m	14.786ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	12.739s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.439m	4.400ms	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	14.523s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.437s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.736s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.914s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.505s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	12.625s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.369s		0	1	0.00
		rom_e2e_jtag_inject_rma	12.571s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.947s		0	1	0.00
V3		TOTAL			0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	23.166m	14.026ms	1	1	100.00
		chip_sw_entropy_src_kat_test	3.368m	3.637ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	3.651m	3.592ms	1	1	100.00
		chip_plic_all_irqs_0	9.073m	5.895ms	1	1	100.00
		chip_plic_all_irqs_10	10.981m	7.635ms	1	1	100.00
		chip_sw_dma_inline_hashing	5.204m	6.169ms	1	1	100.00
		chip_sw_dma_abort	4.456m	3.835ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.645s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.933s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.672s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	12.799s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	12.761s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.803s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.404s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	12.899s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	12.200s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	13.099s		0	1	0.00
		chip_sw_entropy_src_smoketest	4.894m	4.929ms	1	1	100.00
		chip_sw_mbx_smoketest	4.809m	5.799ms	1	1	100.00
		TOTAL			78	250	31.20

Failure Buckets

Job returned non-zero exit code has 134 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.106228492275058518121485963896470864916311334208733530329856871524490542470969
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 118.799s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.39323378717631902935864944675977305929041566336644402642116260830629122511434
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 121.527s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.41203964487482241672893514969715849773438607247087755049573375923625377403251
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 104.220s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.53777028399455021824110331020755079896982643117151028182072308422988597960184
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 107.636s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.33641546194013861427047272201486217773809175093249008553822284483359186992214
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 108.737s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 129 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.13027559009033119043222412764586458112617034034785600876120392316558910772533
    Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.960788070296253643812148952502657410032208266152646141650610172009957285872
    Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.62950363254755707442369496992104077510089871110062540838682451859287162834359
    Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.85376479607089530083170266581002671178558025552056422899763654309468086514968
    Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.66214339444855536906947235780485518640505072151840288115842589692276250613082
    Line 381, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:436) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 5 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.94871688876036486259760614824732732978195644310767985866293544056460655412477
Line 410, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20026.951861 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20026.951861 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.37494038446175417208860954915295138931216683480349818506639485887334267462614
Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18026.904704 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.904704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.84163130839847445137519477179045438569910593262012642100832676582781063531970
Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18026.834873 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.834873 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.110417083603328778371026137665034067500578800004985857663794029656346576710975
Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12018.579242 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.579242 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.80348589831571195001202790353679571306923964382476262933219042842351961815290
Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12026.863145 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.863145 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.63182796011879447403224415787852572105502163962972491214116827163921376522005
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.66292396605286240391319649553308672194412915749990889861780307274801434660966
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.20450377959159376873669970790871839485365850447203209110282691836467392269594
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.60400751588950452378407379626754584343887398316860453354499120206035342016248
Line 418, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 5354.246520 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (7450442274379405159919509508608325735016787089701451068694046038375051105526127586305480568067854224125597371483274702768620206146525023178468021577800796 [0x8e4100d4aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd30817b0257f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 5354.246520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.76821068557310987905700090605074316681213233563767147431720466490113661493075
Line 409, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 8520.616475 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (4297663755752173387245450936299626982124356672403063805813387316993676426147864121516250040030968987301360277829901164554632864959211429635847352356265052 [0x520e8af8aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3d4583a097f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 8520.616475 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:436) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 2 failures:
- Test chip_sw_clkmgr_off_aes_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_aes_trans.25694051671366036030676358514986749461037056688556324220160432065789513974024
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log
```
  UVM_ERROR @ 12018.570031 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.570031 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_hmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_hmac_trans.4460936115433055173073461786002169615453389953586396011756436439474365975161
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
```
  UVM_ERROR @ 12026.770862 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.770862 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.42341798291692431017060293988611484662315780909250120420537798034186425098400
Line 6267, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3069.960861 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'h8c66053f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h26972  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3069.960861 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.38681983117752755842876141702667511303095497349668784336308542788613610701556
Line 6267, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4051.998895 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'h802f6fa2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3b  a_opcode: 'h1  a_user: 'h2488f  d_param: 'h0  d_source: 'h3b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4051.998895 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.67006549650983918440527211822872899925978465085154908744135873697175763005103
    Line 1369, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.45552034180358253171349258835353532710690962018454428864835123206484348812439
    Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4919.237050 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4919.237050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.53745190270853644453224862608455956816094017650242023427347542052158161827612
    Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 4400.408844 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 4400.408844 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 1 failures:
- Test chip_sw_lc_ctrl_raw_to_scrap has 1 failures.
  - 0.chip_sw_lc_ctrl_raw_to_scrap.42612175899898484351779257857030435078331380133849422095796902310087620329124
    Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest/run.log
```
  UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
  UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.16520473591836607988888722774979186324737693214663741530914509729248381417145
    Line 627, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 10463.183563 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 10463.183563 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:52) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time! has 1 failures:
- Test chip_sw_soc_proxy_smoketest has 1 failures.
  - 0.chip_sw_soc_proxy_smoketest.57333093470683030776210583098336645296945988150723534012238632712545837592302
    Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
```
  UVM_ERROR @ 5307.178500 us: (chip_sw_soc_proxy_smoke_vseq.sv:52) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
  UVM_INFO @ 5307.178500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.99781037009616180565404660235144514578497477282097079307482694244077083769319
    Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3528.069630 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3528.069630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.55731042085247777738075390426467988285850660670864989332363608835956784949861
    Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4773.568282 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4773.568282 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.12195972622032621198337508148453319604620978431600026545113336041436120181376
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5014.547625 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5014.547625 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.46843521970835705594238808445146691253953428100293243993186888066010503375874
    Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5379.025726 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5379.025726 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.2076052079849630563030610742932916901685220212792366247390657783473222600557
    Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.39449551550340713726925618271975910242318952575340908595882929513058520906305
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 5100.123548 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 5100.123548 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.57353397833479929216651448350939219320087532489832229222450086790651735917780
    Line 216, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 3086.450460 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40668 read out mismatch
  UVM_INFO @ 3086.450460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.30056500993240960083575339796150345379836006370148790980432018736764491187314
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.72833996788741816705040065832562480433849890923510087620087211946202154537933
    Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 3834.811316 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 3834.811316 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```