CSRNG Simulation Results

Tuesday October 28 2025 16:02:27 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke csrng_smoke 3.000s 175.774us 1 1 100.00
V1 csr_hw_reset csrng_csr_hw_reset 3.000s 30.779us 1 1 100.00
V1 csr_rw csrng_csr_rw 2.000s 25.673us 1 1 100.00
V1 csr_bit_bash csrng_csr_bit_bash 9.000s 421.653us 1 1 100.00
V1 csr_aliasing csrng_csr_aliasing 5.000s 251.212us 1 1 100.00
V1 csr_mem_rw_with_rand_reset csrng_csr_mem_rw_with_rand_reset 1.000s 31.753us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr csrng_csr_rw 2.000s 25.673us 1 1 100.00
csrng_csr_aliasing 5.000s 251.212us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 interrupts csrng_intr 5.000s 117.761us 1 1 100.00
V2 alerts csrng_alert 10.000s 586.609us 1 1 100.00
V2 err csrng_err 2.000s 28.115us 1 1 100.00
V2 cmds csrng_cmds 1.683m 4.526ms 1 1 100.00
V2 life cycle csrng_cmds 1.683m 4.526ms 1 1 100.00
V2 stress_all csrng_stress_all 8.500m 21.871ms 1 1 100.00
V2 intr_test csrng_intr_test 3.000s 89.731us 1 1 100.00
V2 alert_test csrng_alert_test 3.000s 154.268us 1 1 100.00
V2 tl_d_oob_addr_access csrng_tl_errors 6.000s 226.275us 1 1 100.00
V2 tl_d_illegal_access csrng_tl_errors 6.000s 226.275us 1 1 100.00
V2 tl_d_outstanding_access csrng_csr_hw_reset 3.000s 30.779us 1 1 100.00
csrng_csr_rw 2.000s 25.673us 1 1 100.00
csrng_csr_aliasing 5.000s 251.212us 1 1 100.00
csrng_same_csr_outstanding 3.000s 99.512us 1 1 100.00
V2 tl_d_partial_access csrng_csr_hw_reset 3.000s 30.779us 1 1 100.00
csrng_csr_rw 2.000s 25.673us 1 1 100.00
csrng_csr_aliasing 5.000s 251.212us 1 1 100.00
csrng_same_csr_outstanding 3.000s 99.512us 1 1 100.00
V2 TOTAL 9 9 100.00
V2S tl_intg_err csrng_sec_cm 6.000s 201.180us 1 1 100.00
csrng_tl_intg_err 6.000s 133.176us 1 1 100.00
V2S sec_cm_config_regwen csrng_regwen 2.000s 27.648us 1 1 100.00
csrng_csr_rw 2.000s 25.673us 1 1 100.00
V2S sec_cm_config_mubi csrng_alert 10.000s 586.609us 1 1 100.00
V2S sec_cm_intersig_mubi csrng_stress_all 8.500m 21.871ms 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse csrng_intr 5.000s 117.761us 1 1 100.00
csrng_err 2.000s 28.115us 1 1 100.00
csrng_sec_cm 6.000s 201.180us 1 1 100.00
V2S sec_cm_update_fsm_sparse csrng_intr 5.000s 117.761us 1 1 100.00
csrng_err 2.000s 28.115us 1 1 100.00
csrng_sec_cm 6.000s 201.180us 1 1 100.00
V2S sec_cm_blk_enc_fsm_sparse csrng_intr 5.000s 117.761us 1 1 100.00
csrng_err 2.000s 28.115us 1 1 100.00
csrng_sec_cm 6.000s 201.180us 1 1 100.00
V2S sec_cm_outblk_fsm_sparse csrng_intr 5.000s 117.761us 1 1 100.00
csrng_err 2.000s 28.115us 1 1 100.00
csrng_sec_cm 6.000s 201.180us 1 1 100.00
V2S sec_cm_gen_cmd_ctr_redun csrng_intr 5.000s 117.761us 1 1 100.00
csrng_err 2.000s 28.115us 1 1 100.00
csrng_sec_cm 6.000s 201.180us 1 1 100.00
V2S sec_cm_drbg_upd_ctr_redun csrng_intr 5.000s 117.761us 1 1 100.00
csrng_err 2.000s 28.115us 1 1 100.00
csrng_sec_cm 6.000s 201.180us 1 1 100.00
V2S sec_cm_drbg_gen_ctr_redun csrng_intr 5.000s 117.761us 1 1 100.00
csrng_err 2.000s 28.115us 1 1 100.00
csrng_sec_cm 6.000s 201.180us 1 1 100.00
V2S sec_cm_ctrl_mubi csrng_alert 10.000s 586.609us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc csrng_intr 5.000s 117.761us 1 1 100.00
csrng_err 2.000s 28.115us 1 1 100.00
V2S sec_cm_constants_lc_gated csrng_stress_all 8.500m 21.871ms 1 1 100.00
V2S sec_cm_sw_genbits_bus_consistency csrng_alert 10.000s 586.609us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity csrng_tl_intg_err 6.000s 133.176us 1 1 100.00
V2S sec_cm_aes_cipher_fsm_sparse csrng_intr 5.000s 117.761us 1 1 100.00
csrng_err 2.000s 28.115us 1 1 100.00
csrng_sec_cm 6.000s 201.180us 1 1 100.00
V2S sec_cm_aes_cipher_fsm_redun csrng_intr 5.000s 117.761us 1 1 100.00
csrng_err 2.000s 28.115us 1 1 100.00
V2S sec_cm_aes_cipher_ctrl_sparse csrng_intr 5.000s 117.761us 1 1 100.00
csrng_err 2.000s 28.115us 1 1 100.00
V2S sec_cm_aes_cipher_fsm_local_esc csrng_intr 5.000s 117.761us 1 1 100.00
csrng_err 2.000s 28.115us 1 1 100.00
V2S sec_cm_aes_cipher_ctr_redun csrng_intr 5.000s 117.761us 1 1 100.00
csrng_err 2.000s 28.115us 1 1 100.00
csrng_sec_cm 6.000s 201.180us 1 1 100.00
V2S sec_cm_aes_cipher_data_reg_local_esc csrng_intr 5.000s 117.761us 1 1 100.00
csrng_err 2.000s 28.115us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset csrng_stress_all_with_rand_reset 2.200m 6.977ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00