DMA Simulation Results

Tuesday October 28 2025 16:02:27 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	4.000s	264.891us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	4.000s	218.813us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	5.000s	267.622us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	49.830us	1	1	100.00
V1	csr_rw	dma_csr_rw	1.000s	37.502us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	12.000s	1.489ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	3.000s	87.003us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	34.058us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	1.000s	37.502us	1	1	100.00
		dma_csr_aliasing	3.000s	87.003us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.050m	19.254ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	7.517m	133.517ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	26.333m	476.281ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	26.333m	476.281ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	7.517m	133.517ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	1.700m	9.144ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	26.333m	476.281ms	1	1	100.00
V2	dma_abort	dma_abort	4.000s	254.408us	1	1	100.00
V2	dma_stress_all	dma_stress_all	56.000s	16.801ms	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	31.702us	1	1	100.00
V2	intr_test	dma_intr_test	2.000s	124.470us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	2.000s	111.363us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	2.000s	111.363us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	49.830us	1	1	100.00
		dma_csr_rw	1.000s	37.502us	1	1	100.00
		dma_csr_aliasing	3.000s	87.003us	1	1	100.00
		dma_same_csr_outstanding	2.000s	460.583us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	49.830us	1	1	100.00
		dma_csr_rw	1.000s	37.502us	1	1	100.00
		dma_csr_aliasing	3.000s	87.003us	1	1	100.00
		dma_same_csr_outstanding	2.000s	460.583us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	18.000s	330.482us	1	1	100.00
		dma_generic_stress	1.700m	9.144ms	1	1	100.00
		dma_handshake_stress	26.333m	476.281ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	8.000s	624.916us	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	3.000s	212.379us	1	1	100.00
		dma_sec_cm	1.000s	13.057us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.350m	17.809ms	1	1	100.00
		dma_longer_transfer	5.000s	288.768us	1	1	100.00
		dma_stress_all_with_rand_reset	3.000s	404.668us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.89387293028012000058235454409328419751353740349099022398933738329986324711902
      Line 91, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  404668439ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  404668439ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---