EDN Simulation Results

Tuesday October 28 2025 16:02:27 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.900s	26.308us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.840s	18.113us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.990s	13.144us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.450s	249.938us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	0.940s	16.993us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.950s	86.529us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.990s	13.144us	1	1	100.00
		edn_csr_aliasing	0.940s	16.993us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.060s	229.167us	1	1	100.00
V2	csrng_commands	edn_genbits	2.060s	229.167us	1	1	100.00
V2	genbits	edn_genbits	2.060s	229.167us	1	1	100.00
V2	interrupts	edn_intr	0.910s	21.818us	1	1	100.00
V2	alerts	edn_alert	1.050s	86.025us	1	1	100.00
V2	errs	edn_err	0.980s	19.511us	1	1	100.00
V2	disable	edn_disable	0.830s	36.510us	1	1	100.00
		edn_disable_auto_req_mode	1.070s	294.553us	1	1	100.00
V2	stress_all	edn_stress_all	1.230s	161.464us	1	1	100.00
V2	intr_test	edn_intr_test	0.790s	22.978us	1	1	100.00
V2	alert_test	edn_alert_test	0.830s	47.991us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.690s	171.853us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.690s	171.853us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.840s	18.113us	1	1	100.00
		edn_csr_rw	0.990s	13.144us	1	1	100.00
		edn_csr_aliasing	0.940s	16.993us	1	1	100.00
		edn_same_csr_outstanding	1.080s	58.242us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.840s	18.113us	1	1	100.00
		edn_csr_rw	0.990s	13.144us	1	1	100.00
		edn_csr_aliasing	0.940s	16.993us	1	1	100.00
		edn_same_csr_outstanding	1.080s	58.242us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	5.710s	1.011ms	1	1	100.00
		edn_tl_intg_err	2.150s	1.292ms	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.960s	17.746us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.050s	86.025us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	5.710s	1.011ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	5.710s	1.011ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	5.710s	1.011ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	5.710s	1.011ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.050s	86.025us	1	1	100.00
		edn_sec_cm	5.710s	1.011ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.050s	86.025us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.150s	1.292ms	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	7.130s	579.598us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00