HMAC Simulation Results

Tuesday October 28 2025 16:02:27 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 2.360s 153.690us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.820s 28.058us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.870s 25.029us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.690s 1.858ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.490s 157.370us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.420s 164.021us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.870s 25.029us 1 1 100.00
hmac_csr_aliasing 2.490s 157.370us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 1.001m 4.776ms 1 1 100.00
V2 back_pressure hmac_back_pressure 22.680s 2.456ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.303m 19.656ms 1 1 100.00
hmac_test_sha384_vectors 18.880s 208.728us 1 1 100.00
hmac_test_sha512_vectors 6.456m 41.500ms 1 1 100.00
hmac_test_hmac256_vectors 6.400s 2.233ms 1 1 100.00
hmac_test_hmac384_vectors 5.910s 759.710us 1 1 100.00
hmac_test_hmac512_vectors 7.870s 2.071ms 1 1 100.00
V2 burst_wr hmac_burst_wr 16.030s 16.124ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 53.910s 444.516us 1 1 100.00
V2 error hmac_error 24.620s 2.255ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 26.340s 801.584us 1 1 100.00
V2 save_and_restore hmac_smoke 2.360s 153.690us 1 1 100.00
hmac_long_msg 1.001m 4.776ms 1 1 100.00
hmac_back_pressure 22.680s 2.456ms 1 1 100.00
hmac_datapath_stress 53.910s 444.516us 1 1 100.00
hmac_burst_wr 16.030s 16.124ms 1 1 100.00
hmac_stress_all 1.392m 30.944ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 2.360s 153.690us 1 1 100.00
hmac_long_msg 1.001m 4.776ms 1 1 100.00
hmac_back_pressure 22.680s 2.456ms 1 1 100.00
hmac_datapath_stress 53.910s 444.516us 1 1 100.00
hmac_wipe_secret 26.340s 801.584us 1 1 100.00
hmac_test_sha256_vectors 3.303m 19.656ms 1 1 100.00
hmac_test_sha384_vectors 18.880s 208.728us 1 1 100.00
hmac_test_sha512_vectors 6.456m 41.500ms 1 1 100.00
hmac_test_hmac256_vectors 6.400s 2.233ms 1 1 100.00
hmac_test_hmac384_vectors 5.910s 759.710us 1 1 100.00
hmac_test_hmac512_vectors 7.870s 2.071ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 2.360s 153.690us 1 1 100.00
hmac_long_msg 1.001m 4.776ms 1 1 100.00
hmac_back_pressure 22.680s 2.456ms 1 1 100.00
hmac_datapath_stress 53.910s 444.516us 1 1 100.00
hmac_burst_wr 16.030s 16.124ms 1 1 100.00
hmac_error 24.620s 2.255ms 1 1 100.00
hmac_wipe_secret 26.340s 801.584us 1 1 100.00
hmac_test_sha256_vectors 3.303m 19.656ms 1 1 100.00
hmac_test_sha384_vectors 18.880s 208.728us 1 1 100.00
hmac_test_sha512_vectors 6.456m 41.500ms 1 1 100.00
hmac_test_hmac256_vectors 6.400s 2.233ms 1 1 100.00
hmac_test_hmac384_vectors 5.910s 759.710us 1 1 100.00
hmac_test_hmac512_vectors 7.870s 2.071ms 1 1 100.00
hmac_stress_all 1.392m 30.944ms 1 1 100.00
V2 stress_all hmac_stress_all 1.392m 30.944ms 1 1 100.00
V2 alert_test hmac_alert_test 0.650s 12.849us 1 1 100.00
V2 intr_test hmac_intr_test 0.680s 17.219us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.230s 140.487us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.230s 140.487us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.820s 28.058us 1 1 100.00
hmac_csr_rw 0.870s 25.029us 1 1 100.00
hmac_csr_aliasing 2.490s 157.370us 1 1 100.00
hmac_same_csr_outstanding 1.410s 145.853us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.820s 28.058us 1 1 100.00
hmac_csr_rw 0.870s 25.029us 1 1 100.00
hmac_csr_aliasing 2.490s 157.370us 1 1 100.00
hmac_same_csr_outstanding 1.410s 145.853us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.820s 124.042us 1 1 100.00
hmac_tl_intg_err 3.150s 577.846us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.150s 577.846us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 2.360s 153.690us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.660s 99.838us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 10.190s 3.197ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.350s 121.185us 1 1 100.00
TOTAL 28 28 100.00