I2C Simulation Results

Tuesday October 28 2025 16:02:27 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	22.950s	1.668ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	13.490s	642.083us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.910s	18.958us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.920s	18.138us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.300s	420.183us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.140s	51.248us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.200s	72.920us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.920s	18.138us	1	1	100.00
		i2c_csr_aliasing	1.140s	51.248us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.010s	12.672us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	6.092m	23.907ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	45.130s	2.951ms	1	1	100.00
V2	host_override	i2c_host_override	0.720s	29.751us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	47.060s	25.099ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	54.580s	3.070ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.030s	82.156us	1	1	100.00
		i2c_host_fifo_fmt_empty	3.590s	212.591us	1	1	100.00
		i2c_host_fifo_reset_rx	9.600s	264.103us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	30.150s	1.994ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	24.080s	6.640ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.270s	139.446us	1	1	100.00
V2	target_glitch	i2c_target_glitch	3.860s	585.871us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	2.635m	43.682ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.350s	2.421ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	10.270s	752.622us	1	1	100.00
		i2c_target_intr_smoke	3.510s	3.364ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.990s	307.878us	1	1	100.00
		i2c_target_fifo_reset_tx	1.010s	191.714us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	8.648m	47.425ms	1	1	100.00
		i2c_target_stress_rd	10.270s	752.622us	1	1	100.00
		i2c_target_intr_stress_wr	4.180s	13.256ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.110s	6.154ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	3.550s	2.290ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.290s	2.813ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.880s	558.515us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.800s	3.836ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.200s	129.402us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	45.130s	2.951ms	1	1	100.00
		i2c_host_perf_precise	4.530s	874.504us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	24.080s	6.640ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	7.080s	739.017us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.660s	445.864us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.150s	1.195ms	1	1	100.00
		i2c_target_nack_txstretch	1.720s	146.588us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	19.350s	2.615ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.720s	1.885ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.850s	15.303us	1	1	100.00
V2	intr_test	i2c_intr_test	0.720s	18.247us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.080s	284.030us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.080s	284.030us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.910s	18.958us	1	1	100.00
		i2c_csr_rw	0.920s	18.138us	1	1	100.00
		i2c_csr_aliasing	1.140s	51.248us	1	1	100.00
		i2c_same_csr_outstanding	0.990s	77.870us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.910s	18.958us	1	1	100.00
		i2c_csr_rw	0.920s	18.138us	1	1	100.00
		i2c_csr_aliasing	1.140s	51.248us	1	1	100.00
		i2c_same_csr_outstanding	0.990s	77.870us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.070s	154.480us	1	1	100.00
		i2c_sec_cm	1.000s	49.179us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.070s	154.480us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	18.250s	9.009ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.260s	213.982us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	25.320s	906.774us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.71489407503467385239752090994770469406441312064666797960778846077744547698691
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  12672255 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  12672255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.38804449478543695625341910565513476005625720054764400220229419508362932597452
      Line 144, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 23906515345 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 23906515345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.26058689559202359889913535861215571031022055488851294515373540438199569938526
      Line 95, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9008588578 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9008588578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.65582398569686401265336748421513848779509562887171988171561905383392091770262
      Line 94, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 906773543 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 906773543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.1448027472107692376491858386568316042467021664538379541360156958498036614218
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 585871201 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 585871201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.37997467076880886264393795168625314523096495557457574892344563952691830172386
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 213982388 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 128 [0x80])
        UVM_INFO @ 213982388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---