| V1 |
smoke |
keymgr_dpe_smoke |
26.450s |
2.270ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
0.930s |
74.671us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
1.120s |
28.016us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
7.910s |
3.093ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
2.480s |
478.871us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.250s |
84.906us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
1.120s |
28.016us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.480s |
478.871us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
0.790s |
9.570us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
0.850s |
42.839us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
1.400s |
29.174us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
1.400s |
29.174us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
0.930s |
74.671us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.120s |
28.016us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.480s |
478.871us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.200s |
31.449us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
0.930s |
74.671us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.120s |
28.016us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.480s |
478.871us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.200s |
31.449us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
5.730s |
399.352us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
3.030s |
336.659us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
1.600s |
89.212us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
1.600s |
89.212us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
1.600s |
89.212us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
1.600s |
89.212us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
3.320s |
357.412us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
5.730s |
399.352us |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
5.730s |
399.352us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |