KMAC/UNMASKED Simulation Results

Tuesday October 28 2025 16:02:27 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	19.060s	965.468us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.910s	39.048us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.760s	41.929us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.160s	2.884ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.050s	763.866us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.710s	173.874us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.760s	41.929us	1	1	100.00
		kmac_csr_aliasing	6.050s	763.866us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.710s	10.851us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	0.960s	95.021us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	39.090m	740.819ms	1	1	100.00
V2	burst_write	kmac_burst_write	8.377m	31.221ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	23.210s	1.313ms	1	1	100.00
		kmac_test_vectors_sha3_256	18.854m	103.636ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.567m	115.692ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.440s	1.078ms	1	1	100.00
		kmac_test_vectors_shake_128	1.982m	6.736ms	1	1	100.00
		kmac_test_vectors_shake_256	1.624m	28.984ms	1	1	100.00
		kmac_test_vectors_kmac	1.440s	77.692us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.660s	99.858us	1	1	100.00
V2	sideload	kmac_sideload	1.378m	1.639ms	1	1	100.00
V2	app	kmac_app	1.850s	68.842us	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.156m	10.095ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	19.010s	9.412ms	1	1	100.00
V2	error	kmac_error	1.907m	4.487ms	1	1	100.00
V2	key_error	kmac_key_error	4.190s	1.009ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	22.710s	10.205ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	14.430s	2.257ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	6.520s	152.355us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	28.640s	8.870ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.060s	44.482us	1	1	100.00
V2	stress_all	kmac_stress_all	3.542m	37.218ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.690s	18.192us	1	1	100.00
V2	alert_test	kmac_alert_test	0.670s	144.178us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.650s	74.724us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.650s	74.724us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.910s	39.048us	1	1	100.00
		kmac_csr_rw	0.760s	41.929us	1	1	100.00
		kmac_csr_aliasing	6.050s	763.866us	1	1	100.00
		kmac_same_csr_outstanding	1.910s	95.431us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.910s	39.048us	1	1	100.00
		kmac_csr_rw	0.760s	41.929us	1	1	100.00
		kmac_csr_aliasing	6.050s	763.866us	1	1	100.00
		kmac_same_csr_outstanding	1.910s	95.431us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.410s	285.579us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.410s	285.579us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.410s	285.579us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.410s	285.579us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.190s	388.761us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	36.700s	3.672ms	1	1	100.00
		kmac_tl_intg_err	3.470s	270.568us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.470s	270.568us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.060s	44.482us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	19.060s	965.468us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.378m	1.639ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.410s	285.579us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	36.700s	3.672ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	36.700s	3.672ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	36.700s	3.672ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	19.060s	965.468us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.060s	44.482us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	36.700s	3.672ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.117m	18.682ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	19.060s	965.468us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	36.930s	1.965ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.66644424914966204556481968276192924071540261600969313713022080754202332008663
      Line 81, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10204624402 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x16689000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10204624402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---