MBX Simulation Results

Tuesday October 28 2025 16:02:27 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 mbx_smoke mbx_smoke 1.617m 17.841ms 1 1 100.00
V1 csr_hw_reset mbx_csr_hw_reset 9.000s 15.140us 1 1 100.00
V1 csr_rw mbx_csr_rw 8.000s 14.185us 1 1 100.00
V1 csr_bit_bash mbx_csr_bit_bash 10.000s 889.669us 1 1 100.00
V1 csr_aliasing mbx_csr_aliasing 7.000s 17.822us 1 1 100.00
V1 csr_mem_rw_with_rand_reset mbx_csr_mem_rw_with_rand_reset 8.000s 151.435us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr mbx_csr_rw 8.000s 14.185us 1 1 100.00
mbx_csr_aliasing 7.000s 17.822us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 mbx_stress mbx_stress 1.600m 15.497ms 1 1 100.00
V2 mbx_max_activity mbx_stress_zero_delays 11.000s 35.730us 0 1 0.00
V2 mbx_imbx_oob mbx_imbx_oob 1.000m 5.811ms 1 1 100.00
V2 mbx_doe_intr_msg mbx_doe_intr_msg 18.000s 11.826ms 1 1 100.00
V2 alert_test mbx_alert_test 10.000s 22.915us 1 1 100.00
V2 intr_test mbx_intr_test 9.000s 23.483us 1 1 100.00
V2 tl_d_oob_addr_access mbx_tl_errors 12.000s 203.295us 1 1 100.00
V2 tl_d_illegal_access mbx_tl_errors 12.000s 203.295us 1 1 100.00
V2 tl_d_outstanding_access mbx_csr_hw_reset 9.000s 15.140us 1 1 100.00
mbx_csr_rw 8.000s 14.185us 1 1 100.00
mbx_csr_aliasing 7.000s 17.822us 1 1 100.00
mbx_same_csr_outstanding 7.000s 58.468us 1 1 100.00
V2 tl_d_partial_access mbx_csr_hw_reset 9.000s 15.140us 1 1 100.00
mbx_csr_rw 8.000s 14.185us 1 1 100.00
mbx_csr_aliasing 7.000s 17.822us 1 1 100.00
mbx_same_csr_outstanding 7.000s 58.468us 1 1 100.00
V2 TOTAL 7 8 87.50
V2S tl_intg_err mbx_tl_intg_err 11.000s 713.058us 1 1 100.00
mbx_sec_cm 10.000s 17.383us 1 1 100.00
V2S TOTAL 2 2 100.00
TOTAL 15 16 93.75

Failure Buckets