OTBN Simulation Results

Tuesday October 28 2025 16:02:27 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 16.000s 153.629us 0 1 0.00
V1 single_binary otbn_single 18.000s 47.913us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 4.000s 81.495us 1 1 100.00
V1 csr_rw otbn_csr_rw 3.000s 49.399us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 6.000s 74.299us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 3.000s 26.632us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 4.000s 459.188us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 3.000s 49.399us 1 1 100.00
otbn_csr_aliasing 3.000s 26.632us 1 1 100.00
V1 mem_walk otbn_mem_walk 12.000s 711.465us 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 11.000s 220.862us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 16.000s 230.641us 0 1 0.00
V2 multi_error otbn_multi_err 36.000s 686.117us 0 1 0.00
V2 back_to_back otbn_multi 21.000s 84.870us 0 1 0.00
V2 stress_all otbn_stress_all 12.000s 166.111us 0 1 0.00
V2 lc_escalation otbn_escalate 8.000s 120.428us 0 1 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 5.000s 50.561us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 16.000s 42.405us 0 1 0.00
V2 alert_test otbn_alert_test 4.000s 116.347us 1 1 100.00
V2 intr_test otbn_intr_test 3.000s 23.944us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 4.000s 85.650us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 4.000s 85.650us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 4.000s 81.495us 1 1 100.00
otbn_csr_rw 3.000s 49.399us 1 1 100.00
otbn_csr_aliasing 3.000s 26.632us 1 1 100.00
otbn_same_csr_outstanding 3.000s 30.962us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 4.000s 81.495us 1 1 100.00
otbn_csr_rw 3.000s 49.399us 1 1 100.00
otbn_csr_aliasing 3.000s 26.632us 1 1 100.00
otbn_same_csr_outstanding 3.000s 30.962us 1 1 100.00
V2 TOTAL 5 11 45.45
V2S mem_integrity otbn_imem_err 8.000s 22.062us 1 1 100.00
otbn_dmem_err 9.000s 25.859us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 10.000s 223.065us 0 1 0.00
otbn_controller_ispr_rdata_err 12.000s 66.873us 0 1 0.00
otbn_mac_bignum_acc_err 7.000s 63.477us 0 1 0.00
otbn_urnd_err 7.000s 63.114us 0 1 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 9.000s 48.866us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 4.000s 19.673us 0 1 0.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 5.000s 128.266us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 1.617m 1.121ms 1 1 100.00
otbn_tl_intg_err 14.000s 753.211us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 13.000s 198.335us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 1.617m 1.121ms 1 1 100.00
V2S prim_count_check otbn_sec_cm 1.617m 1.121ms 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 16.000s 153.629us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 9.000s 25.859us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 8.000s 22.062us 1 1 100.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 14.000s 753.211us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 8.000s 120.428us 0 1 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 8.000s 22.062us 1 1 100.00
otbn_dmem_err 9.000s 25.859us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 50.561us 1 1 100.00
otbn_illegal_mem_acc 9.000s 48.866us 1 1 100.00
otbn_sec_cm 1.617m 1.121ms 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 1.617m 1.121ms 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 18.000s 47.913us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 8.000s 22.062us 1 1 100.00
otbn_dmem_err 9.000s 25.859us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 50.561us 1 1 100.00
otbn_illegal_mem_acc 9.000s 48.866us 1 1 100.00
otbn_sec_cm 1.617m 1.121ms 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 1.617m 1.121ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 8.000s 120.428us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 8.000s 22.062us 1 1 100.00
otbn_dmem_err 9.000s 25.859us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 50.561us 1 1 100.00
otbn_illegal_mem_acc 9.000s 48.866us 1 1 100.00
otbn_sec_cm 1.617m 1.121ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 1.617m 1.121ms 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 18.000s 47.913us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 7.000s 70.149us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 5.000s 22.809us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 39.000s 120.605us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 39.000s 120.605us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 5.000s 42.222us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 1.617m 1.121ms 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 1.617m 1.121ms 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 6.000s 50.994us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 1.617m 1.121ms 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 1.617m 1.121ms 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 11.000s 22.205us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 11.000s 22.205us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 10.000s 20.669us 0 1 0.00
V2S sec_cm_data_mem_sec_wipe otbn_single 18.000s 47.913us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 18.000s 47.913us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 18.000s 47.913us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 21.000s 84.870us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 18.000s 47.913us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 18.000s 47.913us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 8.000s 76.657us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 18.000s 47.913us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 1.617m 1.121ms 1 1 100.00
V2S TOTAL 7 20 35.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 4.633m 798.699us 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 19 41 46.34

Failure Buckets