ROM_CTRL/32KB Simulation Results

Tuesday October 28 2025 16:02:27 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	3.950s	420.970us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	7.630s	179.923us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	4.940s	129.421us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	4.140s	357.172us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.370s	129.926us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	4.250s	1.939ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	4.940s	129.421us	1	1	100.00
		rom_ctrl_csr_aliasing	4.370s	129.926us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	4.600s	537.743us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	3.770s	690.678us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	4.380s	597.463us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	13.770s	3.118ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	7.340s	556.813us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	4.450s	169.145us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	6.640s	387.002us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	6.640s	387.002us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	7.630s	179.923us	1	1	100.00
		rom_ctrl_csr_rw	4.940s	129.421us	1	1	100.00
		rom_ctrl_csr_aliasing	4.370s	129.926us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.340s	132.772us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	7.630s	179.923us	1	1	100.00
		rom_ctrl_csr_rw	4.940s	129.421us	1	1	100.00
		rom_ctrl_csr_aliasing	4.370s	129.926us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.340s	132.772us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	19.700s	2.120ms	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	20.200s	837.070us	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.691m	1.101ms	0	1	0.00
		rom_ctrl_tl_intg_err	44.950s	1.014ms	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.691m	1.101ms	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	1.691m	1.101ms	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.700s	2.120ms	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.700s	2.120ms	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	19.700s	2.120ms	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.700s	2.120ms	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.700s	2.120ms	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.691m	1.101ms	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.691m	1.101ms	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	3.950s	420.970us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	3.950s	420.970us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	3.950s	420.970us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	44.950s	1.014ms	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	19.700s	2.120ms	0	1	0.00
		rom_ctrl_kmac_err_chk	7.340s	556.813us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	19.700s	2.120ms	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	19.700s	2.120ms	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	19.700s	2.120ms	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	20.200s	837.070us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.691m	1.101ms	0	1	0.00
V2S		TOTAL			2	4	50.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.125m	14.411ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			17	19	89.47

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.53291619849139120081964266353618400957873127218331977062950198281218723279029
      Line 85, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 2120081405 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 2120081405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.26794860916545148330044346220371982786816387896486804355578213655683300829384
      Line 105, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 3182201ps failed at 3182201ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 3182201ps failed at 3182201ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'