ROM_CTRL/64KB Simulation Results

Tuesday October 28 2025 16:02:27 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.280s 313.627us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 13.260s 1.084ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.710s 1.073ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.820s 1.274ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5.870s 864.929us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 9.010s 320.998us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.710s 1.073ms 1 1 100.00
rom_ctrl_csr_aliasing 5.870s 864.929us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.060s 370.353us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.910s 205.686us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.830s 766.558us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 22.300s 813.679us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 18.120s 548.132us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.640s 212.669us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.730s 2.789ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.730s 2.789ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 13.260s 1.084ms 1 1 100.00
rom_ctrl_csr_rw 6.710s 1.073ms 1 1 100.00
rom_ctrl_csr_aliasing 5.870s 864.929us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.590s 301.067us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 13.260s 1.084ms 1 1 100.00
rom_ctrl_csr_rw 6.710s 1.073ms 1 1 100.00
rom_ctrl_csr_aliasing 5.870s 864.929us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.590s 301.067us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.918m 10.589ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 29.690s 3.944ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.822m 861.892us 1 1 100.00
rom_ctrl_tl_intg_err 53.240s 427.597us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.822m 861.892us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.822m 861.892us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.918m 10.589ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.918m 10.589ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.918m 10.589ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.918m 10.589ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.918m 10.589ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.822m 861.892us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.822m 861.892us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.280s 313.627us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.280s 313.627us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.280s 313.627us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 53.240s 427.597us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.918m 10.589ms 1 1 100.00
rom_ctrl_kmac_err_chk 18.120s 548.132us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.918m 10.589ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.918m 10.589ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.918m 10.589ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 29.690s 3.944ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.822m 861.892us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 48.510s 11.376ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00