158897e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 1.060s | 114.764us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.630s | 44.564us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.560s | 12.161us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 1.600s | 144.574us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.890s | 40.728us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 0.760s | 180.300us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.560s | 12.161us | 1 | 1 | 100.00 |
| rv_timer_csr_aliasing | 0.890s | 40.728us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 1.050s | 328.475us | 0 | 1 | 0.00 |
| V2 | disabled | rv_timer_disabled | 2.850s | 2.255ms | 1 | 1 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 7.530s | 28.485ms | 1 | 1 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 7.530s | 28.485ms | 1 | 1 | 100.00 |
| V2 | stress | rv_timer_stress_all | 7.350s | 4.170ms | 1 | 1 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.670s | 35.037us | 1 | 1 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.790s | 22.116us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 1.420s | 266.307us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 1.420s | 266.307us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.630s | 44.564us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.560s | 12.161us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.890s | 40.728us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.890s | 28.262us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.630s | 44.564us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.560s | 12.161us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.890s | 40.728us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.890s | 28.262us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.880s | 64.761us | 1 | 1 | 100.00 |
| rv_timer_tl_intg_err | 0.990s | 107.123us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 0.990s | 107.123us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | min_value | rv_timer_min | 0.790s | 473.557us | 0 | 1 | 0.00 |
| V3 | max_value | rv_timer_max | 0.700s | 49.527us | 0 | 1 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 13.480s | 17.470ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 3 | 33.33 | |||
| TOTAL | 16 | 19 | 84.21 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:
Test rv_timer_min has 1 failures.
0.rv_timer_min.107991070346480406529351272024132108527567750835385674098270875118571143988380
Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 473556813 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb480c304) == 0x1
UVM_INFO @ 473556813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_random_reset has 1 failures.
0.rv_timer_random_reset.2111247084662438208117221963110296163378547397037927903025036862446724931178
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 328474994 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x337fd304) == 0x1
UVM_INFO @ 328474994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:
0.rv_timer_max.4050059479729928058220555426893672149717854569096108122458010770526526953499
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 49527128 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 49527128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---