SPI_DEVICE/1R1W Simulation Results

Tuesday October 28 2025 16:02:27 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	15.150s	1.460ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.990s	66.686us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.090s	39.516us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	24.010s	5.793ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.960s	1.689ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.650s	648.726us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.090s	39.516us	1	1	100.00
		spi_device_csr_aliasing	15.960s	1.689ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.720s	23.692us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.010s	61.999us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.780s	56.749us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.760s	1.750us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.790s	3.130us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	0.830s	22.511us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	0.830s	22.511us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.280s	696.055us	1	1	100.00
		spi_device_tpm_sts_read	0.960s	187.961us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	17.250s	2.366ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.320s	1.950ms	1	1	100.00
		spi_device_flash_all	31.820s	3.605ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.350s	653.729us	1	1	100.00
		spi_device_flash_all	31.820s	3.605ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.350s	653.729us	1	1	100.00
		spi_device_flash_all	31.820s	3.605ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	31.820s	3.605ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.740s	4.105ms	1	1	100.00
		spi_device_flash_all	31.820s	3.605ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.740s	4.105ms	1	1	100.00
		spi_device_flash_all	31.820s	3.605ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.740s	4.105ms	1	1	100.00
		spi_device_flash_all	31.820s	3.605ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.740s	4.105ms	1	1	100.00
		spi_device_flash_all	31.820s	3.605ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.740s	4.105ms	1	1	100.00
		spi_device_flash_all	31.820s	3.605ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	18.040s	37.771ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	1.018m	18.396ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.018m	18.396ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.018m	18.396ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.290s	247.812us	1	1	100.00
		spi_device_read_buffer_direct	7.460s	1.369ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.018m	18.396ms	1	1	100.00
		spi_device_flash_all	31.820s	3.605ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	31.820s	3.605ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	31.820s	3.605ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.110s	32.960us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.110s	32.960us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	15.150s	1.460ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	49.870s	7.818ms	1	1	100.00
V2	stress_all	spi_device_stress_all	9.840s	1.054ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.100s	49.426us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.020s	15.081us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.150s	128.869us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.150s	128.869us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.990s	66.686us	1	1	100.00
		spi_device_csr_rw	2.090s	39.516us	1	1	100.00
		spi_device_csr_aliasing	15.960s	1.689ms	1	1	100.00
		spi_device_same_csr_outstanding	1.570s	54.701us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.990s	66.686us	1	1	100.00
		spi_device_csr_rw	2.090s	39.516us	1	1	100.00
		spi_device_csr_aliasing	15.960s	1.689ms	1	1	100.00
		spi_device_same_csr_outstanding	1.570s	54.701us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.200s	179.325us	1	1	100.00
		spi_device_tl_intg_err	6.530s	356.135us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.530s	356.135us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	17.270s	5.149ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.38943094389808621404059377953128269149291019675898229861835021605736017575158
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1191362 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[57])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1191362 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1191362 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[953])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.82108614200021354016581690628937756938548879900082124928064813097064080305645
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    898526 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc47935 [110001000111100100110101] vs 0x0 [0])
        UVM_ERROR @    940526 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x708736 [11100001000011100110110] vs 0x0 [0])
        UVM_ERROR @    969526 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x16e6fa [101101110011011111010] vs 0x0 [0])
        UVM_ERROR @   1029526 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb6ff91 [101101101111111110010001] vs 0x0 [0])
        UVM_ERROR @   1051526 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xec4c5 [11101100010011000101] vs 0x0 [0])