SPI_HOST Simulation Results

Tuesday October 28 2025 16:02:27 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	39.000s	2.686ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	55.418us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	20.530us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	217.246us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	103.159us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	1.000s	71.850us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	20.530us	1	1	100.00
		spi_host_csr_aliasing	1.000s	103.159us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	53.444us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	45.120us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	46.319us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	1.443ms	1	1	100.00
		spi_host_error_cmd	1.000s	28.928us	1	1	100.00
		spi_host_event	10.000s	365.618us	1	1	100.00
V2	clock_rate	spi_host_speed	7.000s	183.401us	1	1	100.00
V2	speed	spi_host_speed	7.000s	183.401us	1	1	100.00
V2	chip_select_timing	spi_host_speed	7.000s	183.401us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	2.000s	33.698us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.000s	46.897us	1	1	100.00
V2	cpol_cpha	spi_host_speed	7.000s	183.401us	1	1	100.00
V2	full_cycle	spi_host_speed	7.000s	183.401us	1	1	100.00
V2	duplex	spi_host_smoke	39.000s	2.686ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	39.000s	2.686ms	1	1	100.00
V2	stress_all	spi_host_stress_all	2.000s	39.165us	1	1	100.00
V2	spien	spi_host_spien	10.000s	4.540ms	1	1	100.00
V2	stall	spi_host_status_stall	48.000s	1.521ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	32.000s	1.801ms	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	1.443ms	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	18.203us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	22.283us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	71.580us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	71.580us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	55.418us	1	1	100.00
		spi_host_csr_rw	1.000s	20.530us	1	1	100.00
		spi_host_csr_aliasing	1.000s	103.159us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	22.324us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	55.418us	1	1	100.00
		spi_host_csr_rw	1.000s	20.530us	1	1	100.00
		spi_host_csr_aliasing	1.000s	103.159us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	22.324us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	183.028us	1	1	100.00
		spi_host_sec_cm	2.000s	70.633us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	183.028us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	1.850m	5.783ms	1	1	100.00
		TOTAL			26	26	100.00