SRAM_CTRL/MAIN Simulation Results

Tuesday October 28 2025 16:02:27 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	40.850s	3.171ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.990s	20.889us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.020s	13.464us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.290s	350.522us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.950s	41.109us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.220s	822.469us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.020s	13.464us	1	1	100.00
		sram_ctrl_csr_aliasing	0.950s	41.109us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.003m	55.312ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.628m	1.610ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.310m	8.365ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.283m	5.250ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	11.604m	53.800ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.412m	19.902ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	23.190s	5.398ms	1	1	100.00
V2	executable	sram_ctrl_executable	5.328m	12.451ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	16.440s	974.038us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.065m	52.436ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	35.930s	763.102us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	6.390s	698.173us	1	1	100.00
		sram_ctrl_throughput_w_readback	28.510s	1.662ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	10.390m	15.017ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.330s	676.004us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	35.509m	26.387ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.900s	10.761us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.110s	145.688us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.110s	145.688us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.990s	20.889us	1	1	100.00
		sram_ctrl_csr_rw	1.020s	13.464us	1	1	100.00
		sram_ctrl_csr_aliasing	0.950s	41.109us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.710s	25.587us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.990s	20.889us	1	1	100.00
		sram_ctrl_csr_rw	1.020s	13.464us	1	1	100.00
		sram_ctrl_csr_aliasing	0.950s	41.109us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.710s	25.587us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	29.630s	12.549ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.830s	4.206us	0	1	0.00
		sram_ctrl_tl_intg_err	2.190s	418.091us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.830s	4.206us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.190s	418.091us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	10.390m	15.017ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	10.390m	15.017ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.020s	13.464us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.328m	12.451ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.328m	12.451ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.328m	12.451ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	23.190s	5.398ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.550s	716.565us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	29.630s	12.549ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	8.130s	697.280us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	40.850s	3.171ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	40.850s	3.171ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.328m	12.451ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.830s	4.206us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	23.190s	5.398ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.830s	4.206us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.830s	4.206us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	40.850s	3.171ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.830s	4.206us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.430m	3.116ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.83990675647936730031024090722983452556324328209003751396280007443828839082428
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4205615 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4205615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---