UART Simulation Results

Tuesday October 28 2025 16:02:27 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.360s	527.532us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.780s	22.718us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.600s	53.623us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.920s	520.415us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.990s	19.881us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.130s	20.549us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.600s	53.623us	1	1	100.00
		uart_csr_aliasing	0.990s	19.881us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	5.110s	7.358ms	1	1	100.00
V2	parity	uart_smoke	1.360s	527.532us	1	1	100.00
		uart_tx_rx	5.110s	7.358ms	1	1	100.00
V2	parity_error	uart_intr	6.560s	23.910ms	1	1	100.00
		uart_rx_parity_err	26.290s	73.440ms	1	1	100.00
V2	watermark	uart_tx_rx	5.110s	7.358ms	1	1	100.00
		uart_intr	6.560s	23.910ms	1	1	100.00
V2	fifo_full	uart_fifo_full	4.017m	145.147ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	23.920s	19.229ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	55.250s	30.678ms	1	1	100.00
V2	rx_frame_err	uart_intr	6.560s	23.910ms	1	1	100.00
V2	rx_break_err	uart_intr	6.560s	23.910ms	1	1	100.00
V2	rx_timeout	uart_intr	6.560s	23.910ms	1	1	100.00
V2	perf	uart_perf	58.940s	7.321ms	1	1	100.00
V2	sys_loopback	uart_loopback	5.510s	6.774ms	1	1	100.00
V2	line_loopback	uart_loopback	5.510s	6.774ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	19.240s	18.220ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.300s	5.900ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.660s	305.470us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	31.770s	5.380ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	5.109m	136.254ms	1	1	100.00
V2	stress_all	uart_stress_all	1.220m	168.783ms	1	1	100.00
V2	alert_test	uart_alert_test	0.620s	125.851us	1	1	100.00
V2	intr_test	uart_intr_test	0.800s	34.131us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.600s	187.513us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.600s	187.513us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.780s	22.718us	1	1	100.00
		uart_csr_rw	0.600s	53.623us	1	1	100.00
		uart_csr_aliasing	0.990s	19.881us	1	1	100.00
		uart_same_csr_outstanding	0.840s	17.224us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.780s	22.718us	1	1	100.00
		uart_csr_rw	0.600s	53.623us	1	1	100.00
		uart_csr_aliasing	0.990s	19.881us	1	1	100.00
		uart_same_csr_outstanding	0.840s	17.224us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	0.960s	41.010us	1	1	100.00
		uart_tl_intg_err	1.010s	176.846us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.010s	176.846us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	24.010s	2.471ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00