CHIP Simulation Results

Tuesday October 28 2025 16:02:27 UTC

GitHub Revision: `158897e`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.543m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.543m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	36.166s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	13.640s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	12.833s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.065m	6.743ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.065m	6.743ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.065m	6.743ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	31.810s	10.360us	0	1	0.00
		chip_sw_example_manufacturer	2.355m		0	1	0.00
		chip_sw_example_concurrency	4.143m	5.234ms	1	1	100.00
		chip_sw_uart_smoketest_signed	11.403s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.710s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	8.950s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	8.950s		0	1	0.00
V1	xbar_smoke	xbar_smoke	9.900s	13.634us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.444m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	13.728m	9.171ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.622m	5.195ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	12.963s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	12.964s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	12.405s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	12.481s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.250s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.250s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.076m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.661m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.099m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.099m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.730m	3.842ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.920m	4.191ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.327m	7.659ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.864s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.814s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.714m	11.111ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	7.041m	6.467ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	25.994m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	25.994m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	15.531s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.854m	5.202ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.854m	5.202ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.612m	18.018ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.544m	5.102ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.761m	5.377ms	1	1	100.00
		chip_sw_aes_idle	5.002m	5.372ms	1	1	100.00
		chip_sw_hmac_enc_idle	5.269m	5.849ms	1	1	100.00
		chip_sw_kmac_idle	5.116m	5.753ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.444m	12.018ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	14.998m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	13.286m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	14.016m	12.019ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	12.193s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.386s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.954s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.538s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.958s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.441s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.663s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.193s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.386s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.954s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.538s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.958s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.441s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.663s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	13.602s		0	1	0.00
		chip_sw_aes_enc_jitter_en	38.400s	10.200us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	41.780s	10.340us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	40.110s	10.260us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	37.880s	10.120us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	15.125s		0	1	0.00
		chip_sw_clkmgr_jitter	4.850m	5.612ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	5.334m	5.925ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.207s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	39.900s	10.220us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	43.980s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	39.450s	10.120us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	41.560s	10.240us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	36.390s	10.140us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.446s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	12.018s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.762s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	13.354s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	23.148m	16.558ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.360m	10.474ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.854m	5.202ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	13.428s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.360m	10.474ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	14.419s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	12.032s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	11.215s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	11.961s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.697s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	23.148m	16.558ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.327m	7.659ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	24.924m	20.018ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.521m	6.081ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	10.253m	8.327ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.319m	4.907ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	23.148m	16.558ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	13.834s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.559s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	23.148m	16.558ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	13.116s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	10.253m	8.327ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	14.143s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.522s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.787s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.573s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	12.790s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.563s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.559s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	12.222s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	12.225s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.222s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.222s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.222s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.687m	7.784ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.614s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.266s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.408s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	13.036s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.222s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	8.761m	10.105ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	10.652m	10.705ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	13.586s		0	1	0.00
		chip_prim_tl_access	14.139m	27.349ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.193s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.386s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.954s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.538s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.958s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.441s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.663s		0	1	0.00
		chip_rv_dm_lc_disabled	6.714m	11.111ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.428m	5.834ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	38.400s	10.200us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.639m	4.811ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.002m	5.372ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.211m	3.905ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	41.780s	10.340us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.269m	5.849ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.226m	5.152ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.397m	4.689ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	37.880s	10.120us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	8.761m	10.105ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.222s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	33.530s	10.240us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.501m	4.932ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.116m	5.753ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	15.089s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	15.089s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.289s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.195m	3.696ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	16.520s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	8.761m	10.105ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	40.110s	10.260us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	17.153s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	13.602s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.761m	5.377ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.761m	5.377ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.761m	5.377ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.654m	6.719ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	10.652m	10.705ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	10.652m	10.705ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	9.434m	10.654ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	15.125s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.586s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	23.148m	16.558ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.099m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.222s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.654m	6.719ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.761m	10.105ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.434m	10.654ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.086m	4.179ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.654m	6.719ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.761m	10.105ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.434m	10.654ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.086m	4.179ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.222s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.813s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	12.225s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.614s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.266s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.408s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	13.036s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.222s		0	1	0.00
		chip_prim_tl_access	14.139m	27.349ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	14.139m	27.349ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	11.920s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	13.028s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	12.018s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	13.602s		0	1	0.00
		chip_sw_aes_enc_jitter_en	38.400s	10.200us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	41.780s	10.340us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	40.110s	10.260us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	37.880s	10.120us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	15.125s		0	1	0.00
		chip_sw_clkmgr_jitter	4.850m	5.612ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.737m	8.467ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.737m	8.467ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.913m	5.158ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.810m	4.403ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.584m	4.070ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.295m	4.663ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.572m	5.619ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.105m	3.836ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.086m	4.179ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	24.924m	20.018ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	24.924m	20.018ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	4.078m	4.921ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.118m	5.736ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.465m	5.348ms	1	1	100.00
		chip_sw_csrng_smoketest	3.227m	4.154ms	1	1	100.00
		chip_sw_gpio_smoketest	4.448m	4.522ms	1	1	100.00
		chip_sw_hmac_smoketest	5.152m	5.829ms	1	1	100.00
		chip_sw_kmac_smoketest	4.397m	4.558ms	1	1	100.00
		chip_sw_otbn_smoketest	4.602m	4.065ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.690m	4.038ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.225m	4.290ms	1	1	100.00
		chip_sw_rv_timer_smoketest	5.304m	5.507ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.194m	4.600ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.981m	4.427ms	1	1	100.00
		chip_sw_uart_smoketest	3.713m	5.521ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	17.050s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	11.403s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.444m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.565s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.213m	3.715ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.425m	4.797ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.877m	5.372ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.670m	6.026ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	15.227s		0	1	0.00
		chip_rv_dm_lc_disabled	6.714m	11.111ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.770s		0	1	0.00
		chip_sw_lc_walkthrough_prod	12.530s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	15.575s		0	1	0.00
		chip_sw_lc_walkthrough_rma	12.376s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	15.227s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	7.856m	9.632ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	7.937m	9.881ms	1	1	100.00
		rom_volatile_raw_unlock	12.970s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.538s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	56.348s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.169m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.234m	3.912ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.234m	3.912ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	8.950s		0	1	0.00
		chip_same_csr_outstanding	9.030s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	8.950s		0	1	0.00
		chip_same_csr_outstanding	9.030s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	3.689m	583.294us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.810s	13.074us	1	1	100.00
		xbar_smoke_large_delays	5.011m	2.537ms	1	1	100.00
		xbar_smoke_slow_rsp	5.598m	1.968ms	1	1	100.00
		xbar_random_zero_delays	48.130s	44.362us	1	1	100.00
		xbar_random_large_delays	7.385m	3.717ms	1	1	100.00
		xbar_random_slow_rsp	31.662m	11.866ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.625m	197.506us	1	1	100.00
		xbar_error_and_unmapped_addr	1.814m	226.143us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	36.000s	34.771us	1	1	100.00
		xbar_error_and_unmapped_addr	1.814m	226.143us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	4.138m	635.590us	1	1	100.00
		xbar_access_same_device_slow_rsp	38.418m	14.421ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	2.836m	471.712us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	25.083m	3.738ms	1	1	100.00
		xbar_stress_all_with_error	26.065m	4.229ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	2.057m	44.963us	1	1	100.00
		xbar_stress_all_with_reset_error	20.929m	867.684us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.208s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.434s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	13.127s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	12.048s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.991s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.866s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12.689s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	14.428s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	13.590s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.815s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	14.995s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.784s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.914s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	48.910s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	41.591s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	44.629s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	37.809s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	28.274s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	44.785s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	44.772s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	55.204s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	44.936s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	44.301s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	44.993s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	35.673s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	41.067s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	37.837s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	33.977s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	19.236s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.109s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	19.809s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	17.708s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.206s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	13.760s		0	1	0.00
		rom_e2e_asm_init_dev	13.146s		0	1	0.00
		rom_e2e_asm_init_prod	12.644s		0	1	0.00
		rom_e2e_asm_init_prod_end	13.027s		0	1	0.00
		rom_e2e_asm_init_rma	11.986s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.948s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.652s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.481s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.763s		0	1	0.00
V2		TOTAL			68	205	33.17
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.854m	5.258ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.973m	4.911ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.006s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.514s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.039s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.821s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	23.148m	16.558ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	12.179s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.662m	5.159ms	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	11.503s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.067s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.006s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.514s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.039s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	12.428s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.350s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.612s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.851s		0	1	0.00
V3		TOTAL			0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	22.268m	14.561ms	1	1	100.00
		chip_sw_entropy_src_kat_test	3.891m	3.820ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	3.913m	4.693ms	1	1	100.00
		chip_plic_all_irqs_0	9.192m	7.540ms	1	1	100.00
		chip_plic_all_irqs_10	11.601m	6.233ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.429m	5.145ms	1	1	100.00
		chip_sw_dma_abort	3.960m	4.633ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	12.195s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	12.144s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.323s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.738s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.518s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.447s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	12.160s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.777s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.241s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.851s		0	1	0.00
		chip_sw_entropy_src_smoketest	4.655m	3.612ms	1	1	100.00
		chip_sw_mbx_smoketest	5.269m	6.339ms	1	1	100.00
		TOTAL			81	250	32.40

Failure Buckets

Job returned non-zero exit code has 134 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.102686233384570214381926237954743816161484116907158217670852744383376987323807
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 127.310s, Critical Path: 0.03s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.27909067206783990888000241575238548001538495813379711581066125851276834356
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 113.162s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.101520455560262089125536255420437531239104689603503487322412018643630447848472
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 113.120s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.18775134378824708772832418975821684830494348438260364059839321318446952493757
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 89.188s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.81714215407318845352754118696506450594031095113914398581550925027378006227023
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 82.252s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 129 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.88408099006649228738253567517028072066850114246294704458200681617732129828978
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.33088556741095705044294247354548417886052190865665831438939884926760154152382
    Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.31930899017155057514607257269958233265938989620909756020806571934652727722564
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.90237602350257837622309176203018160159179616915587069195811651058352442739821
    Line 375, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.69758896947410820743863414610716644609160736035288314415108784052415185496964
    Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:436) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.19618227808622040535381870425314806327736759243982962124833800430109334862027
Line 421, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.499089 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.499089 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.11513305522379386891621449836020469910393481434863441194095227523143666133456
Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.402492 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.402492 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.82241528928561109789682538065260019295960041216414125667881970649020327171117
Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.496077 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.496077 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.105165677753403677753274072066778747520390411140346598045741651080532396058638
Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12018.481125 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.481125 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.25084399514241946107484530770763712896491641768453466214891776546311904847096
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.32802229021020603479014467963784491334505455112895336868088534506144522572209
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.30394268777355591323346194652621590446858396608719300266741205482170912476032
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.81003359202455380883253248622551041066960406139674363369136534102112104563871
Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 10104.935432 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (6131454672114828748462324713932052856751150937607558763982397031422698206934029154331958957221405268277892424572945627505711248588085052247867717562227804 [0x7511ed17aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3f3475de67f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 10104.935432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.88930282439030164251188587464876736592079147704184470194432289662715307697780
Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 7784.306810 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (6377196204988120652542937785675600924840804455776640447676253425663054971789676920095565137794265974985597566782660437115548854810007409318134504992627804 [0x79c315f2aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3ff95a5037f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 7784.306810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:436) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 2 failures:
- Test chip_sw_clkmgr_off_kmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_kmac_trans.61128591751404343779257912838111395743709622662125438760384868285960035167165
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
```
  UVM_ERROR @ 12026.790023 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.790023 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_otbn_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_otbn_trans.93254386004941523736008898344652399489785054199921464959006604773898716872717
    Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log
```
  UVM_ERROR @ 12018.694562 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.694562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.57913959574050043597042869967759161717472033681218384177041560984894706898237
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3842.333589 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'ha1f02c3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h1  a_user: 'h2489a  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3842.333589 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.62977336886259544948117468520500162955606864273662645382804649358107348261783
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4190.599210 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'h57280229  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h0  a_user: 'h26942  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4190.599210 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.61565828356484922916402148926262974493401265822361255410973949110895819888082
    Line 1348, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.56309379888160501020246500795017935104732117580506030038170028741437146657059
    Line 412, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5194.563954 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5194.563954 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.91906915532007562422324007890264120122862679614588975718266550922131034169157
    Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 5159.124690 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 5159.124690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.114083289613429197756376030861656856616740160547669166787207521448230128299923
    Line 628, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 8327.255864 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 8327.255864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.10480839211590424376247685396609305359215808425533340378382871979658294321001
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5158.066940 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5158.066940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.55666563489177326326047943376325723863756410718770082644479568710692256245914
    Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4403.494227 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4403.494227 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.1134401894496528894306946604536402569133630929171346287083645571893197111520
    Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5201.916086 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5201.916086 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.86519077622444901894803271593007482223624974709477643387538901168350712543883
    Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4662.882730 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4662.882730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.13842894424821057292081116304067604559884523385087625608441068963156807232988
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.88000981020252274936029842852359758702841579859386768323282882274737840769372
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3912.027030 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3912.027030 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:436) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = * ns has 1 failures:
- Test chip_sw_clkmgr_off_hmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_hmac_trans.57574940514714524783168808764919466607844178671902089678168557803840671488013
    Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
```
  UVM_ERROR @ 12018.554309 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.554309 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.64021270412684820068408927273661535046839493818809691282400482172475596667424
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.99535198867407710753878248250980957703154968727708706877466100049316781538127
    Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4633.138542 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4633.138542 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```