| V1 |
smoke |
aon_timer_smoke |
0.980s |
531.693us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
aon_timer_csr_hw_reset |
0.930s |
660.983us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
aon_timer_csr_rw |
0.910s |
507.710us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
aon_timer_csr_bit_bash |
4.180s |
5.878ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
aon_timer_csr_aliasing |
0.980s |
398.030us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
aon_timer_csr_mem_rw_with_rand_reset |
1.000s |
478.186us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
aon_timer_csr_rw |
0.910s |
507.710us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
0.980s |
398.030us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
aon_timer_mem_walk |
1.280s |
442.021us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
aon_timer_mem_partial_access |
0.750s |
380.744us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
prescaler |
aon_timer_prescaler |
1.080s |
582.508us |
1 |
1 |
100.00 |
| V2 |
jump |
aon_timer_jump |
0.810s |
552.301us |
1 |
1 |
100.00 |
| V2 |
stress_all |
aon_timer_stress_all |
42.140s |
81.666ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
aon_timer_alert_test |
1.120s |
304.173us |
1 |
1 |
100.00 |
| V2 |
intr_test |
aon_timer_intr_test |
0.760s |
384.458us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
aon_timer_tl_errors |
1.480s |
404.990us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
aon_timer_tl_errors |
1.480s |
404.990us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
aon_timer_csr_hw_reset |
0.930s |
660.983us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
0.910s |
507.710us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
0.980s |
398.030us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
0.980s |
1.401ms |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
aon_timer_csr_hw_reset |
0.930s |
660.983us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
0.910s |
507.710us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
0.980s |
398.030us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
0.980s |
1.401ms |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
7 |
7 |
100.00 |
| V2S |
tl_intg_err |
aon_timer_sec_cm |
4.710s |
4.341ms |
1 |
1 |
100.00 |
|
|
aon_timer_tl_intg_err |
4.260s |
8.199ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
aon_timer_tl_intg_err |
4.260s |
8.199ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
max_threshold |
aon_timer_smoke_max_thold |
0.750s |
622.290us |
1 |
1 |
100.00 |
| V3 |
min_threshold |
aon_timer_smoke_min_thold |
0.680s |
624.300us |
1 |
1 |
100.00 |
| V3 |
wkup_count_hi_cdc |
aon_timer_wkup_count_cdc_hi |
6.740s |
3.767ms |
1 |
1 |
100.00 |
| V3 |
custom_intr |
aon_timer_custom_intr |
0.660s |
638.455us |
1 |
1 |
100.00 |
| V3 |
alternating_on_off |
aon_timer_alternating_enable_on_off |
8.580s |
4.174ms |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
aon_timer_stress_all_with_rand_reset |
7.850s |
2.987ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
|
|
TOTAL |
|
|
23 |
23 |
100.00 |